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Prof Basant Mohanty

vidwan id: 286579
Male

Director,
Sambalpur University

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 99
Books 0
Proceedings 0

Publications

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Scopus

Citations 1416
h-index 18

CrossRef

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Citations 146
h-index 7
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Professional Recognition

2018

2018 Sydney Parker Award, 2018 M.N.S. Swamy Best Paper Award among all paper published in 2017 and 2018

Circuits, Systems and Signal Processing

Community & Membership

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Institution of Electronics and Telecommunication Engineers (IETE) New Delhi

2012
Life Member

IEEE Circuits and Systems Society

2008
Senior Member

Bio

VLSI for Signal Processing Algorithm and Architecture, Approximate Computing

Personal Details

  • Male
  • Director , Sambalpur University
  • Jyoti Vihar, Burla, Odisha, India
PhD
Berhampur University 2000
M.Sc
Sambalpur University 1989
B.Sc
Other Institute 1987
Intermediate Science
Other Institute 1985
Director Aug 2021 – Present
Sambalpur University
Associate Dean Mar 2019 – Aug 2021
SVKMs NMIMS Mukesh Patel School of Technology Management & Engineering
Professor Jul 2018 – Feb 2019
SVKMs NMIMS Mukesh Patel School of Technology Management & Engineering
Professor Aug 2007 – Jun 2018
Jaypee University of Engeenering & Technology, Guna | Department of Electronics and Communication Engineering
Associate Professor Jul 2005 – Jul 2007
Jaypee University of Engeenering & Technology, Guna | Department of Electronics and Communication Engineering
Assistant Professor Aug 2003 – Jun 2005
Jaypee University of Engeenering & Technology, Guna | Department of Electronics and Communication Engineering
Assistant Professor Jul 2002 – Jul 2003
Mody University of Science and Technology | School of Engineering and Technology
Lecturer Sep 2001 – Jul 2002
Birla Institute of Technology and Science | Department of Electrical and Electronics engineering
Junior Lecturer Oct 1992 – Aug 2001
SKCG (Autonomous) College, Parlakhemundi

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Co-Authors (12)

Vikas

Dr Vikas Tiwari

ORIENTAL UNIVERSITY

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Prof Ganpati Panda

CV Raman College of Engineering (CVRCE), Bhubaneswar

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Dr Gaurav Saxena

Jaypee University of Engeenering & Technology, Guna

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National Institute of Technology, Meghalaya

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Dr Niladri Bihari Puhan

Indian Institute of Technology Bhubaneswar

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Prof Pramod Meher

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Dr Rehan Ahmad

Narsee Monjee Institute of Management Studies, Mumbai

Subodh Kumar

Dr Subodh Kumar Singhal

Jaypee University of Engeenering & Technology, Guna

Sujit Kumar

Dr Sujit Kumar Patel

Thapar Institute of Engineering & Technology

Vasundhara

Dr Vasundhara V

National Institute of Technology Warangal

Vivek

Dr Vivek Chaturvedi

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Scholarly Work

Design and Implementation of Low-Complexity Wavelet Encoder using Approximate Computations for Wireless Visual Sensor Network Applications

Funding Agency: Science and Engineering Research Board

Principal Investigator

2,456,400

2021 - Ongoing

Ongoing

Memory-efficient concurrent VLSI architecture for two-dimensional discrete wavelet transform

University Jaypee University of Engineering and Technology Guna Madhya Pradesh
Year 2014

High-performance VLSI Architecture for FIR Adaptive Filter

University Jaypee University of Engineering and Technology Guna Madhya Pradesh
Year 2016

Scalable Architecture for VLSI implementation of DSP Algorithms

University Jaypee University of Engineering and Technology Guna Madhya Pradesh
Year 2017

Efficient VLSI Architecture for DWT and DWPT based on data-path study

University Jaypee University of Engineering and Technology Guna Madhya Pradesh
Year 2017

Parallel VLSI Architecture for lifting 2-D DWT using radix-8 Booth multiplier

University Jaypee University of Engineering and Technology Guna Madhya Pradesh
Year 2017
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Scholarly Publications

Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters

Open Access
Article
Authors: Mohanty B.K.;Meher P.K.;Al-Maadeed S.;Amira A.

Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation

Open Access
Article

Modified probabilistic estimation bias formulation for hardware efficient fixed-width Booth multiplier

Open Access
ARTICLE
Authors: B.K.Mohanty and VikasTiwari

Area-delay-power efficient carry select adder

Open Access
ARTICLE
Authors: B. K. Mohanty and S. K. Patel

Efficient integer DCT architecture forHEVC

Open Access
ARTICLE
Authors: P.K. Meher, S.Y. Park, B. K. Mohanty, L.K. Seong and Y. C. Hao

Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier

Open Access
Article

Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters

Open Access
ARTICLE
Authors: B. K. Mohanty, P.K. Meher, S.A. Madeed, and A. Amira

Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits

Open Access
Conference Paper
Authors: Meher P.;Mohanty B.;Srikanthan T.