Ministry of Education
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Dr Rutu Parekh

vidwan id: 283954
Female

Associate Professor, ICT
Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar

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Expertise

  • Nanoscience and Nanotechnology

Publications

Total Articles 81
Books 0
Proceedings 0

Publications

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Scopus

Citations 196
h-index 6

CrossRef

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Citations 183
h-index 6
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Professional Recognition

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Community & Membership

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Bio

Nanoelectronics, Microelectronics, Embedded Systems and IOT

Personal Details

  • Female
  • Associate Professor , Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar
  • DA-IICT, Near Indroda Circle, Gandhinagar
PhD
Other Institute 2003
PhD
Other Institute 2003
Associate Professor Jun 2015 – Present
Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar | ICT
Associate Professor Jun 2015 – Present
Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar | ICT

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Co-Authors (8)

Amit

Prof Amit Bhatt

Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar

Bakul

Dr Bakul Gohel

Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar

Girish Kumar

Dr Girish Kumar Mekala

Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh

Monika

Ms Monika Shah

Institute of Technology, Nirma University

Rajeevan

Prof Rajeevan Chandel

National Institute of Technology, Hamirpur

Rasika N.

Dr Rasika N. Dhavse

S.V. National Institute of Technology

Vinay

Dr Vinay Palaparthy

Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar

Yash

Dr Yash Agrawal

Dhirubhai Ambani Institute of Information & Communication Technology (DAIICT), Gandhinagar

Scholarly Work

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Scholarly Publications

Noise removing filters and its implementation on FPGA

Open Access
Conference Paper
Year: 2018. Volume: 475 , Pages: 481-489 .
Authors: Mishra A.;Parekh R.
DOI 10.1007/978-981-10-8240-5_54
3 3

Contemporary On-chip System Modeling using FDTD in Low Power Regime

Open Access
Conference Paper
Year: 2018.
Authors: Agrawal Y.;Chandel R.;Girish M.;Parekh R.
DOI 10.1109/EDAPS.2018.8680862

Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects

Open Access
Conference Paper
Year: 2018.
Authors: Pathade T.;Shah U.;Agrawal Y.;Parekh R.
DOI 10.1109/EDAPS.2018.8680882
5 5

Design and optimization of single electron transistor based 4-bit arithmetic and logic unit at room temperature operation

Open Access
Conference Paper
Year: 2017. Volume: 2018-February , Pages: 34-39 .
Authors: Joshi R.;Parekh R.;Agrawal Y.
DOI 10.1109/iNIS.2017.17
2 1

Single-precision floating point matrix multiplier using low-power arithmetic circuits

Open Access
Book Chapter
Year: 2017. Volume: 436 , Pages: 683-691 .
Authors: Gargave S.;Agrawal Y.;Parekh R.
DOI 10.1007/978-981-10-4394-9_67
2 2

Performance analysis of current-mode interconnect system in presence of process, voltage, and temperature variations

Open Access
Book Chapter
Year: 2017. Volume: 436 , Pages: 543-551 .
Authors: Agrawal Y.;Parekh R.;Chandel R.
DOI 10.1007/978-981-10-4394-9_53
1 1

SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit

Open Access
Article
Microelectronics Journal. Year: 2014. Volume: 45 , Issue: 8 , Pages: 1087-1092 .
Authors: Parekh R.;Beauvais J.;Drouin D.
DOI 10.1016/j.mejo.2014.05.020
15 17

Simulation and design methodology for hybrid SET-CMOS integrated logic at 22-nm room-temperature operation

Open Access
Article
IEEE Transactions on Electron Devices. Year: 2012. Volume: 59 , Issue: 4 , Pages: 918-923 .
Authors: Parekh R.;Beaumont A.;Beauvais J.;Drouin D.
DOI 10.1109/TED.2012.2183374
27 28