Ministry of Education
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Prof Rajagopalan Devanathan

vidwan id: 276775
Male

Emeritus Professor, Department of Electrical and Electronics Engineering
Hindustan Institute of Technology and Science, Kancheepuram

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 104
Books 0
Proceedings 0

Publications

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Scopus

Citations 353
h-index 10

CrossRef

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Citations 186
h-index 7
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Bio

Electrical and Electronics Engineering

Personal Details

  • Male
  • Emeritus Professor , Hindustan Institute of Technology and Science, Kancheepuram
  • Department of Electrical and Electronics Engineering,Hindustan Institute of Technology and Science
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Emeritus Professor Nov 2004 – Present
Hindustan Institute of Technology and Science, Kancheepuram | Department of Electrical and Electronics Engineering

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Co-Authors (3)

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A

Dr A Rajasekar

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Hindustan Institute of Technology and Science, Kancheepuram

Scholarly Work

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Scholarly Publications

Comparison of different approaches for matrix vector multiplication on transputer network - a performance analysis

Open Access
Conference Paper
Year: 1993. Volume: 1 , Pages: 396-401 .
Authors: Kok C.;Devanathan R.;Er M.

Maximum robust stabilizability bound for a SISO system with uncertain time delay

Open Access
Article
Year: 1993. Volume: 9 , Issue: 3 , Pages: 629-637 .
Authors: Devanathan R.

An expert autotuner for multiloop SISO controllers

Open Access
Article
Control Engineering Practice. Year: 1993. Volume: 1 , Issue: 6 , Pages: 999-1008 .
Authors: Kar-Ann Toh ., R. Devanathan .,
DOI 10.1016/0967-0661(93)90010-O
5 6

Temporal logic programming for assembly sequence planning

Open Access
Article
Artificial Intelligence in Engineering. Year: 1993. Volume: 8 , Issue: 4 , Pages: 253-263 .
Authors: Kiam Tian Seow ., R. Devanathan .,
DOI 10.1016/0954-1810(93)90008-4
5 8

Temporal logic formulation of assembly sequence properties

Open Access
Conference Paper
Year: 1992. Volume: 2 , Pages: 1208-1213 .
Authors: Tian S.;Devanathan R.
8

Process identification through stable closed loop response

Open Access
Conference Paper
Year: 1992. Volume: 1 , Pages: 471-475 .
Authors: K.A. Toh ., R. Devanathan .,
DOI 10.1109/SICICI.1992.641821

A Temporal Logic Framework For Assembly Sequence Planning

Open Access
Conference Paper
Year: 1992. Volume: 3 , Pages: 2103-2109 .
Authors: R. Devanathan .,
DOI 10.1109/IROS.1992.601949
2

Assembly sequence planning for odd form component insertion on printed circuit boards using and/or graphs

Open Access
Conference Paper
Year: 1992. Volume: 1 , Pages: 278-282 .
Authors: R. Sasidharan ., R. Devanathan .,
DOI 10.1109/SICICI.1992.641713
3 1