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Dr K V Gowreesrinivas

vidwan id: 264457
Male

Assistant Professor, Electronics and Communication Engineering
Anil Neerukonda Institute Of Technology & Sciences, Visakhapatnam

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 25
Books 0
Proceedings 0

Publications

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Scopus

Citations 53
h-index 5

CrossRef

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Citations 33
h-index 3
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Professional Recognition

2015

VISVESVARAYA FELLOWSHIP

MeitY

Community & Membership

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IEEE

2024
PROFESSIONAL

IEEE

2021
Professional

Bio

DIGITAL VISL, SIGNAL PROCESSING, FPGA BASED SYSTEM DESIGN

Personal Details

  • Male
  • Assistant Professor , Anil Neerukonda Institute Of Technology & Sciences, Visakhapatnam
  • Anil Neerukonda Institute of Technology and Sciences, Near Three Temples, Sangivalasa, Bheemunipatnam(MD)
PhD
Other Institute 2019
Assistant Professor Jun 2013 – Present
Anil Neerukonda Institute Of Technology & Sciences, Visakhapatnam | Electronics and Communication Engineering

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Co-Authors (6)

Anil

Prof Anil Kumar

Indian Institute of Technology Roorkee

Bhaskara Rao

Dr Bhaskara Rao Jana

Anil Neerukonda Institute Of Technology & Sciences, Visakhapatnam

Anil Kumar

Dr Anil Kumar

Indian Institute of Technology Roorkee

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Dr Samundiswary P.

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Mr Srinivasanaidu Nalla

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Scholarly Work

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Scholarly Publications

Design And Evaluation Of Energy-Efficient Approximate Multipliers Authors

Open Access
article
Authors: K V Gowreesrinivas , Ganesh Laveti, Chukka.Anoosha, Eswara Chaitanya Duvvuri, P Chaya Devi, P Devi Pradeep

Design And Implementation Of Power Efficient Multiplier Using Reversible Logic

Open Access
conference paper
Authors: K. Yashoda; K V Gowreesrinivas; M Uma Mahesh; K S V L D Sai Phanindra; Aman Syed; S Sai

Performance Optimized 32-bit Multiplier: Integrating Vedic and Karatsuba Techniques

Open Access
conference paper
Authors: K. V. Gowreesrinivas; B. Vennela; L. Sasank; A. Sai Raghav; D. Venkata Satyanarayana

Optimizing Power Consumption: CSD-Based 16-Bit Multiplier for Low-Power Systems

Open Access
conference paper
Authors: K. V. Gowreesrinivas; S. Rahul; K. Arjun; B. Sushma; Ch. Mohan Sai

FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders

Open Access
Article
Authors: Gowreesrinivas K.V.;Sabbavarapu S.;Samundiswary P.

FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors

Open Access
INPROCEEDINGS
Authors: Sairam, P and Manikumar, K and Reddy, Y Suresh and Narayana, B Uday and Gowreesrinivas, K.V.

Design and Implementation of Hybrid Full Adder Based 16-bit Multiplication Using FPGA

Open Access
INPROCEEDINGS
Authors: Gowreesrinivas, K.V. and Sri, B.Usha and Saideepak, S. and Tarun, G. and Sagar, I.Sathya

Improvised hierarchy of floating point multiplication using 5:3 compressor

Open Access
Article