Ministry of Education
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Dr Ramanjaneyulu Ningampalli

vidwan id: 245488
Male

Associate Professor, Department of Electronics and Communication Engineering
Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal

Orchid Icon 0000-0001-5276-6997 Google Scholar Icon 57202233284 Researcher Icon ADX-3844-2022 Google Scholar Icon hnglvw0AAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 19
Books 0
Proceedings 0

Publications

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Scopus

Citations 21
h-index 2

CrossRef

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Citations 5
h-index 1
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Professional Recognition

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Community & Membership

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IETE

2007
Associate Member

Bio

Design and Analysis of CMOS based analog VLSI circuits.

Personal Details

  • Male
  • Associate Professor , Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal
  • Department of Electronics and Communication Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal
Ph.D
Other Institute 2019
M.Tech
Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal 2010
B.Tech
Sree Vidyanikethan Engineering College 2004
Associate Professor Sep 2004 – Present
Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal | Department of Electronics and Communication Engineering

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Co-Authors (9)

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Dr M V Ganeswara Rao

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Dr Jayachandra Prasad Talari

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Scholarly Work

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Scholarly Publications

PERFORMANCE ANALYSIS OF INTERCONNECT CIRCUIT TECHNIQUES FOR HIGH-SPEED VLSI INTERCONNECTS

Open Access
journal-article
Year: 2022.
Authors: Manjula Jayamma ., N. Ramanjaneyulu ., Rama Subbaiah Boya ., Y. Mallikarjuna Rao .,
DOI 10.17148/ijarcce.2022.111202

Analysis of Crosstalk in Coupled On-Chip VLSI Interconnects

Open Access
journal-article
Year: 2022.
Authors:
DOI 10.5281/ZENODO.7413063

Analysis of Crosstalk in GNR-Based Global Interconnects

Open Access
journal-article
Year: 2022.
Authors:
DOI 10.5281/ZENODO.7431946

Crosstalk Analysis of SLGNR-Based VLSI Interconnects

Open Access
journal-article
Year: 2022.
Authors:
DOI 10.5281/ZENODO.7472762

ANALYSIS OF A DELAY CELL BASED VOLTAGE CONTROLLED RING OSCILLATOR IN CMOS

Open Access
journal-article
JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES. Year: 2020.
Authors: N Ramanjaneyulu .,
DOI 10.26782/jmcms.spl.5/2020.01.00028

A 3.4 GHZ fast-locking PLL using transmission gate charge-pump In 0.18μm CMOS for HDMI applications

Open Access
Article
ARPN Journal of Engineering and Applied Sciences. Year: 2018. Volume: 13 , Issue: 8 , Pages: 2815-2829 .
Authors: Ningampalli R.;Donti S.;Kodati S.P.
1

Design of a Three Stage Ring VCO in 0.18 µm CMOS under PVT Variations

Open Access
journal-article
Year: 2017.
Authors: N. Ramanjaneyulu ., D. Satyanarayana ., K. Satya .,
DOI 10.5120/ijca2017914932

Design of a 3.4 GHz Wide-Tuning-Range VCO in 0.18 μm CMOS

Open Access
Book Chapter
Year: 2017. Volume: 5 , Pages: 227-234 .
Authors: Ningampalli Ramanjaneyulu ., Donti Satyanarayana ., Kodati Satya Prasad .,
DOI 10.1007/978-981-10-3226-4_22
1