Ministry of Education
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Dr Gavaskar Kanagaraj

vidwan id: 236138
Male

Assistant Professor, Department of Electronics and Communication Engineering
Kongu Engineering College, Erode

Orchid Icon 0000-0003-4432-339X Google Scholar Icon 56418377700 Researcher Icon AAL-4922-2020 Google Scholar Icon WJigc_IAAAAJ

Expertise

  • Telecommunications

Publications

Total Articles 25
Books 0
Proceedings 0

Publications

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Scopus

Citations 34
h-index 4

CrossRef

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Citations 51
h-index 2
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Professional Recognition

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Community & Membership

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Bio

VLSI Design

Personal Details

  • Male
  • Assistant Professor , Kongu Engineering College, Erode
  • Kongu Engineering College
Ph.D
Other Institute 2020
Assistant Professor May 2013 – Present
Kongu Engineering College, Erode | Department of Electronics and Communication Engineering

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Co-Authors (7)

Archana

Dr Archana Chaugule

Pimpri Chinchwad Education Trust`s Pimpri Chinchwad College of Engineering and Research, Ravet

Arulmurugan

Dr Arulmurugan Azhaganantham

Kongu Engineering College, Erode

Kavita

Kavita Jain

Swami Keshwanand Institute of Technology, Management & Gramothan, Jaipur

Malathi

Dr Malathi D

Kongu Engineering College, Erode

Kavitha

Ms Kavitha N S

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Ragupathy

Dr Ragupathy U S

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Mr Ravivarma Govindaraj

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Scholarly Work

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Scholarly Publications

Proposed Design of 1 KB Memory Array Structure for Cache Memories

Open Access
journal-article
Wireless Personal Communications. Year: 2019. Volume: 109 , Issue: 2 , Pages: 823-847 .
Authors: Gavaskar, K.;Ragupathy, U.S.;Malini, V.
5

Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Open Access
journal-article
Wireless Personal Communications. Year: 2019. Volume: 108 , Issue: 4 , Pages: 2311-2339 .
Authors: Gavaskar, K.;Ragupathy, U.S.;Malini, V.
DOI 10.1007/s11277-019-06523-7
22

Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

Open Access
journal-article
Analog Integrated Circuits and Signal Processing. Year: 2019. Volume: 100 , Issue: 1 , Pages: 61-77 .
Authors: Gavaskar, K.;Ragupathy, U.S.
DOI 10.1007/s10470-018-1277-3
27

Proposed Design of 1 KB Memory Array Structure for Cache Memories

Open Access
journal-article
Wireless Personal Communications. Year: 2019.
Authors:

Foundation of Computer Science (FCS), NY, USA

Open Access
article
Year: 2019. Volume: 6 , Pages: 248-251 .
Authors: Jitendra Sharma and Kavita Jain

Design of novel SRAM cell using Hybrid VLSI techniques for low power and high speed in embedded memories

Open Access
conference-paper
Year: 2018. Pages: 22-32 .
Authors: Gavaskar, K.;Ragupathy, U.S.;Malathi, D.;Ravivarma, G.
DOI 10.1109/I2C2SW45816.2018.8997525
2

Functional verification environment for I2C master controller using system verilog

Open Access
Conference Paper
Year: 2017.
Authors: Sukhanya M.;Gavaskar K.
DOI 10.1109/ICSCN.2017.8085732
7

An efficient design and analysis of low power SRAM memory cell for ULTRA applications

Open Access
journal-article
Asian Journal of Research in Social Sciences and Humanities. Year: 2017.
Authors: