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Dr Tarun Kumar Agarwal

vidwan id: 231567
Male

Assistant Professor (Grade-I), Electrical Engineering
Indian Institute of Technology Gandhinagar

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 53
Books 0
Proceedings 0

Publications

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Scopus

Citations 606
h-index 16

CrossRef

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Citations 556
h-index 14
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Bio

Benchmarking of beyond CMOS materials and devices using multi-scale approaches, Modeling and simulation of advanced nanoscale devices, Material-Device-Circuit co-design for alternative computing paradigms.

Personal Details

  • Male
  • Assistant Professor (Grade-I) , Indian Institute of Technology Gandhinagar
  • Palaj, Gujarat, India
Ph.D
KU Leuven 2018
M. Tech.
Indian Institute of Technology Delhi 2010
B. Tech.
Aligarh Muslim University 2008
Assistant Professor (Grade-I) Apr 2021 – Present
Indian Institute of Technology Gandhinagar | Electrical Engineering
Post-Doctoral Fellow Aug 2018 – Mar 2021
Eidgenössische Technische Hochschule (ETH), Zurich
Research Scholar Jul 2013 – Mar 2014
Independent
Senior Research Fellow Jul 2012 – May 2013
Indian Institute of Technology Bombay
Engineer Jul 2010 – Jun 2012
Intel Labs

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Co-Authors (19)

Balvinder Kaur

Dr Balvinder Kaur Sapra

Bhabha Atomic Research Centre (BARC), Mumbai

Rishi Pal

Dr Rishi Pal Chauhan

National Institute of Technology Kurukshetra

Dipankar

Dr Dipankar Saha

Indian Institute of Technology Bombay

Mohd Asif

Dr Mohd Asif Hasan

Aligarh Muslim University

Jhuma

Dr Jhuma Saha

Indian Institute of Technology Gandhinagar

Jagadesh Kumar

Prof Jagadesh Kumar Mamidala

Indian Institute of Technology Delhi

M. Jagadesh

Prof M. Jagadesh Kumar

University Grant Commission

Mohd

Prof Mohd Hasan

Aligarh Muslim University

Mohd

Prof Mohd Hasan

Aligarh Muslim University

Oves

Dr Oves Badami

Indian Institute of Technology Hyderabad

Praveen

Dr Praveen Aggarwal

National Institute of Technology Kurukshetra

Santanu

Prof Santanu Chaudhury

Indian Institute of Technology Delhi

Swaroop

Dr Swaroop Ganguly

Indian Institute of Technology Bombay

Souvik

Dr Souvik Mahapatra

Indian Institute of Technology Bombay

Sudeep

Dr Sudeep Kumara K

Dayananda Sagar University, Bangalore

O

Prof O Uma Maheswari

Anna University

Scholarly Work

Material-device-circuil co-design of two-dimensional materials vertical heterostructures for future computing and memory devices

Funding Agency: IIT Gandhinagar

PI

63,00,000

2021 - Ongoing

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Bilayer graphene tunneling field effect transistor

A. Nourbakhsh
B. Soree
M. Heyns
T. K. Agarwal
Engineering and Technology Patent No. : US9293536 Filed : 16-12-2014
Published : 22-03-2016 Granted

Scholarly Publications

Design optimization of gate-all-around vertical nanowire transistors for future memory applications

Open Access
Conference Paper
Authors: Agarwal T.;Badami O.;Ganguly S.;Mahapatra S.;Saha D.

A dc model for partially depleted SOI laterally diffused MOSFETs utilizing the HiSIM-HV compact model

Open Access
Article

Modeling of partially depleted SOI DEMOSFETs with a sub-circuit utilizing the HiSIM-HV compact model

Open Access
Conference Paper

Compact modeling of partially depleted silicon-on-insulator drain-extended MOSFET (DEMOSFET) including high-voltage and floating-body effects

Open Access
Article

Performance comparison of static CMOS and MCML gates in sub-threshold region of operation for 32nm CMOS technology

Open Access
Conference Paper
Authors: Agarwal T.K.;Sawhney A.;Kureshi A.K.;Hasan M.