Ministry of Education
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Mr Sisir Kumar Jena

vidwan id: 229627
Male

,

Orchid Icon 0000-0001-8788-1581 Google Scholar Icon 57212342636 Researcher Icon ABG-5910-2021

Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 9
Books 0
Proceedings 0

Publications

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Scopus

Citations 19
h-index 3

CrossRef

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Citations 9
h-index 2
Google Scholar

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Professional Recognition

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Community & Membership

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IEEE Membership

Student Membership

IEEE Young Professionals

Student Membership

IEEE Computer Society Membership

Student Membership

International Roadmap for Devices and Systems Community, IEEE

Student Membership

Test Technology Technical Council, IEEE Computer Society

Student Membership

Bio

Digital VLSI Design and Testing

Personal Details

  • Male
  • DIT University, Mussoorie-Diversion Road, Village Makkawala, Dehradun
Ph.D. (cont.)
Indian Institute of Technology Guwahati 2021
M.Tech
KIIT Deemed to be University, Bhubaneswar 2010
Assistant Professor Aug 2019 – May 2022
DIT University | School of Computing
Assistant Professor Jul 2007 – Jul 2015
Nalanda Institute of Technology (NIT), Bhubaneswar

Related Profiles

Experts (0)

Pragati

Ms Pragati Mishra

Assistant Professor

Sridhar

Dr Sridhar Sekar

Assistant Professor

DEEPAK

Mr DEEPAK B N

N/A

Md

Dr Md Nadeem M

Assistant Professor

Rashmi

Rashmi Chandra

Assistant Professor

Anjali

Dr Anjali Jadhav

Doctor

Abhishek

Mr Abhishek Shukla

Assistant Professor (Grade-I)

N

Dr N PRAKASH

Assistant Professor

Mrinmoy

Mr Mrinmoy Sadhukhan

Research Scholar

Haranath

Mr Haranath Rakshit

Junior Research Fellow

Organisation (0)

no data

Co-Authors (2)

Jatindra Kumar

Prof Jatindra Kumar Deka

Indian Institute of Technology Guwahati

Santosh

Prof Santosh Biswas

Indian Institute of Technology, Bhilai

Scholarly Work

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Scholarly Publications

A robust approach for digital watermarking of satellite imagery dataset

Open Access
article
Year: 2022. Volume: 7 , Pages: 82--93 .
Authors: Husain, Arshad and Mishra, Aditya Dev and Jena, Sisir Kumar

Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement

Open Access
Article
Year: 2021. Volume: 37 , Issue: 5-6 , Pages: 633-652 .
Authors: Jena S.K.;Biswas S.;Deka J.K.
DOI 10.1007/s10836-021-05980-y
5 5

Analysis and Redesign of Digital Circuits to Support Green Computing Through Approximation

Open Access
book-chapter
Year: 2021.
Authors:
DOI 10.1007/978-981-15-7533-4_11

C Programming: Learn to Code

Open Access
book
Year: 2021.
Authors:

Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis

Open Access
Conference Paper
Year: 2020.
Authors: Jena S.K.;Biswas S.;Deka J.K.
DOI 10.1109/VDAT50263.2020.9190571
2

Maximizing yield through retesting of rejected circuits using approximation technique

Open Access
Conference Paper
Year: 2020. Volume: 2020-November , Pages: 182-187 .
Authors: Jena S.K.;Biswas S.;Deka J.K.
DOI 10.1109/TENCON50793.2020.9293891
8

Fault Classification Based Approximate Testing of Digital VLSI Circuit

Open Access
Conference Paper
Year: 2020. Volume: 686 , Pages: 641-651 .
Authors: Jena S.K.
DOI 10.1007/978-981-15-7031-5_61
1

Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application

Open Access
Conference Paper
Year: 2019. Volume: 11942 LNCS , Pages: 561-570 .
Authors: Jena S.;Biswas S.;Deka J.
DOI 10.1007/978-3-030-34872-4_62
4 3