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Dr Subhendu Kumar Sahoo

vidwan id: 228735
Male

Professor, Department of Electrical and Electronics engineering
Birla Institute of Technology and Science

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 72
Books 0
Proceedings 0

Publications

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Scopus

Citations 806
h-index 13

CrossRef

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Citations 671
h-index 12
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Professional Recognition

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Community & Membership

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Bio

Research Interest VLSI Arithmetic circuits for signal processing applications. Digital VLSI circuits for communication application.

Personal Details

  • Male
  • Professor , Birla Institute of Technology and Science
  • Hyderabad Campus Jawaharnagar, Kapra Mandal
Ph.D
Other Institute 2006
Professor Jul 1999 – Present
Birla Institute of Technology and Science | Department of Electrical and Electronics engineering

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Organisations (1053+)

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Co-Authors (13)

Abhijit Rameshwar

Prof Abhijit Rameshwar Asati

Birla Institute of Technology and Science

Akhilesh

Dr Akhilesh Gupta

Indian Institute of Technology Roorkee

Anu

Dr Anu Gupta

Birla Institute of Technology and Science

Apurva

Dr Apurva Kumari

Padmasri Dr. B.V Raju Institute of Technology

Chandra

Dr Chandra Shekhar

Birla Institute of Technology and Science

Chandra

Dr Chandra Shekhar

Birla Institute of Technology and Science

Chinnaiah

Dr Chinnaiah M C

Padmasri Dr. B.V Raju Institute of Technology

Khairunnisa

Dr Khairunnisa Amreen

St. Anns Degree College for Women (Mehdipatnam)

Manoj Kumar

Dr Manoj Kumar Majumder

Dr Shyama Prasad Mukherjee International Institute of Information Technology, Naya Raipur

Pramod

Prof Pramod Meher

CV Raman College of Engineering (CVRCE), Bhubaneswar

Rahul Dev

Prof Rahul Dev Mishra

National Institute of Technology Silchar

Sanket

Prof Sanket Goel

Birla Institute of Technology and Science

Venkateswarlu

Dr Venkateswarlu Gonuguntla

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Scholarly Work

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High performance vlsi architecture for digital fir filter design

University Birla Institute of Technology and Science Pilani
Year 2015

AN ELECTROCHEMICAL MICROFLUIDIC DEVICE AND A PROCESS FOR PREPARING THE SAME

Birla Institute Of Technology & Science (BITS)
Pilani
Biological Sciences Application No. : 202111059663 Filed : 21-12-2021
Published : 23-06-2023 Filed

Scholarly Publications

An efficient RNS-FIR filter implementation using the moduli set {2 <sup>k</sup> - 1, 2<sup>k</sup>, 2<sup>k-1</sup> - 1}

Open Access
Conference Paper
Authors: Kotha S.R.;Singhvi A.;Sahoo S.K.

A high speed FIR filter architecture based on novel higher radix algorithm

Open Access
Conference Paper
Authors: Sahoo S.K.;Srinivasa R.K.

A high speed, high Radix 32-bit Redundant parallel multiplier

Open Access
Conference Paper
Authors: Srinivasa Reddy K.;Sahoo S.;Chakraborty S.

Design of low power, high performance FIR filter using modified differential evolution algorithm

Open Access
Conference Paper
Authors: Reddy K.S.;Bharath M.S.;Sahoo S.K.;Sinha S.;Reddy J.P.

Delay optimized array multiplier for signal and image processing

Open Access
Conference Paper
Authors: Sahoo S.K.;Shekhar C.

A fast final adder for a 54-bit parallel multiplier for DSP application

Open Access
Article

Computation sharing multiplier using redundant binary arithmetic

Open Access
Conference Paper
Authors: Kumar Kattamuri R.;Sahoo S.

A novel redundant binary number to natural binary number converter

Open Access
Article