Ministry of Education
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Dr Ramaseshagiri Rao Vadrevu

vidwan id: 217327
Male

Assistant Professor, Electronics and Communication Engineering
Institute of Aeronautical Engineering

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 11
Books 0
Proceedings 0

Publications

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Scopus

Citations 262
h-index 4

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ISTE

2021
LIFE MEMBER

IETE

2008
FELLOW

Bio

Digital Systems

Personal Details

  • Male
  • Assistant Professor , Institute of Aeronautical Engineering
  • Institute of Aeronautical Engineering, Dundigal Road, Dundigal
PhD
JNTUH College of Engineering Hyderabad 2023
MASTER OF ENGINEERING
Osmania University 1991
Assistant Professor Feb 2007 – Present
Institute of Aeronautical Engineering | Electronics and Communication Engineering

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Co-Authors (7)

Arulananth

Dr Arulananth T S

MLR Institute of Technology

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Mr Chaitanya Kancharapu

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A SYSTEM FOR VLSI LAYOUT OPTIMIZATION IN CONNECTED AND PYRAMID NETWORKS USING DEEP LEARNING

1)Ms.Arelli Shruthi Address of Applicant :Assistant Professor
Department of Electronics and Communication Engineering
St Peter's Engineering College
Hyderabad
Telangana
India. Pin Code:500100 ----------- ----------- 2)Dr.M.Sadees 3)Mr.Akula Trinadha Rao 4)Dr.V.R.Seshagiri Rao 5)Mrs.D.V.N. Bharathi
Engineering and Technology Patent No. : Dr.V.R.Seshagiri Rao Filed : 22-09-2024
Published : 04-10-2024 Published

AUTOMATED IMAGE ENHANCEMENT USING AI-DRIVEN CONTEXTUAL ANALYSIS

Dr.V.R.Seshagiri Rao_Institute of Aeronautical Engineering Hyderabad
Engineering and Technology Patent No. : 202441028399 Filed : 06-04-2024
Published : 12-04-2024 Published

SCALABLE DISTRIBUTED DENIAL OF SERVICE (DDOS) PROTECTION MECHANISM WITH DYNAMIC RESOURCE ALLOCATION AND TRAFFIC REDIRECTION STRATEGIES

Dr.V.R.Seshagiri Rao_Institute of Aeronautical Engineering_Hyderabad
Engineering and Technology Patent No. : 202441020869 Filed : 19-03-2024
Published : 29-03-2024 Published

A SYSTEM FOR VIDEO FIGURE RETRIEVAL BASED ON DEEP LEARNING AND METHOD THEREOF

Dr.V. R.Seshagiri Rao_Institute of Aeronautical Engineering
Engineering and Technology Patent No. : The Patent Office Journal No. 50/2021 Dated 10/12/2021 Filed : 01-12-2021
Published : 10-12-2021 Published

Scholarly Publications

Implementation of IEEE 802.11p for Vehicular Communication: Utilizing NI USRP N321 to Advance Mobile Interactive Technologies

Open Access
Article
Year: 2025. Volume: 19 , Issue: 9 , Pages: 19-30 .
Authors: Telagam N.;Ajay Kumar Y.L.;Seshagiri Rao V.R.;Nanjundan M.;Chaithanya S.;Kandasamy N.
DOI 10.3991/ijim.v19i09.52259

Efficient Built in Self Repair for Multiple RAMs

Open Access
Conference Paper
Year: 2023.
Authors: Rao V.R.S.;Rani M.A.
DOI 10.1109/I2CT57861.2023.10126119
3

Design of High-Performance Full Adder Using 20nm CNTFET Technology

Open Access
Conference Paper
Year: 2022. Pages: 192-196 .
Authors: G. Naveen;V.R Seshagiri Rao;Nirmala. N;Pavan Kalyan. L;Vallabhuni Vijay;S. China Venkateswarlu;Rajeev Ratna Vallabhuni
DOI 10.1109/ICRTCST54752.2022.9782042
17

High-Performance IIR Filter Implementation Using FPGA

Open Access
Conference Paper
Year: 2022. Pages: 354-358 .
Authors: Vijay V.;Seshagiri Rao V.R.;Chaitanya K.;China Venkateshwarlu S.;Pittala C.S.;Vallabhuni R.R.
DOI 10.1109/ICRTCST54752.2022.9781944
18

Self Healing Memory Using 2D Spares

Open Access
Conference Paper
Year: 2021. Pages: 695-699 .
Authors: Seshagiri Rao V.R.;Rani M.A.
DOI 10.1109/ICCMC51019.2021.9418409
2

Local and Global Spare structure for Repair of Multiblock memories

Open Access
article
Year: 2020. Volume: 13 , Pages: 1170-1183 .
Authors: V.R.Seshagiri Rao

Global block level redundancy scheme for repair of clustered fault cells

Open Access
Article
Year: 2019. Volume: 8 , Issue: 3 , Pages: 399-402 .
Authors: Poornachandra P.;Seshagiri Rao V.
DOI 10.30534/ijatcse/2019/10832019

Redundancy algorithm using line based method for memories achieving less area overhead

Open Access
Article
Year: 2018. Volume: 8 , Issue: 2 Special Issue 2 , Pages: 474-479 .
Authors: Seshagiri Rao V.;Asha Rani M.
2