Ministry of Education
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Dr Sushant Mittal

vidwan id: 215336
Male

Assistant Professor, Department of Electronics Engineering
Indian Institute of Technology (BHU), Varanasi

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 25
Books 0
Proceedings 0

Publications

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Scopus

Citations 145
h-index 8

CrossRef

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Citations 131
h-index 8
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Bio

Semiconductor Logic And Memory Devices, Design Technology Co-Optimization (DTCO), Variability Modeling Of Devices

Personal Details

  • Male
  • Assistant Professor , Indian Institute of Technology (BHU), Varanasi
  • Indian Institute of Technology (Banaras Hindu University)
PhD
Other Institute 2016
Assistant Professor Jul 2020 – Present
Indian Institute of Technology (BHU), Varanasi | Department of Electronics Engineering

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Co-Authors (6)

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Prof Apurba Laha

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Dr Swaroop Ganguly

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Scholarly Work

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Scholarly Publications

Junctionless accumulation-mode SOI ferroelectric FinFET for synaptic weights

Open Access
Article
Microelectronics Journal. Year: 2024. Volume: 153 .
Authors: Singh R.;Mittal S.;Verma S.
DOI 10.1016/j.mejo.2024.106413

FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement

Open Access
Article
IEEE Transactions on Electron Devices. Year: 2022. Volume: 69 , Issue: 12 , Pages: 6699-6704 .
Authors: Singh R.;Verma S.;Mittal S.
DOI 10.1109/TED.2022.3217206
4

Via size optimization for optimum circuit performance at 3 nm node

Open Access
Conference Paper
Year: 2020. Volume: 2020-September , Pages: 327-330 .
Authors: Mittal S.;Pal A.;Saremi M.;Bazizi E.M.;Alexander B.;Ayyagari B.
DOI 10.23919/SISPAD49475.2020.9241685
1 1

Impact of mol/beol air-spacer on parasitic capacitance and circuit performance at 3 nm node

Open Access
Conference Paper
Year: 2019. Volume: 2019-September .
Authors: Pal A.;Mittal S.;Bazizi E.M.;Sachid A.;Saremi M.;Colombeau B.;Thareja G.;Lin S.;Alexander B.;Natarajan S.;Ayyagari B.
DOI 10.1109/SISPAD.2019.8870410
10 12

Highly-Doped Through-Contact Silicon Epi Design at 3 nm node

Open Access
Conference Paper
Year: 2019. Volume: 2019-June , Pages: 55-56 .
Authors: Mittal S.;Pal A.;Saremi M.;Ferrell J.;Haverty M.;Miyashita T.;Kim N.;Bazizi E.M.;Alexander B.;Sachid A.B.;Ayyagari B.
DOI 10.1109/DRC46940.2019.9046479
1 1

Scaling NC-FinFET to sub-3 nm nodes

Open Access
Conference Paper
Year: 2018.
Authors: Pal A.;Mittal S.;Ghosh B.;Lin C.Y.;Alexander B.;Ayyagari B.;Sachid A.B.
DOI 10.1109/S3S.2018.8640184

The first compact model to determine VT distribution for DG-FinFET due to LER

Open Access
Article
IEEE Transactions on Electron Devices. Year: 2018. Volume: 65 , Issue: 11 , Pages: 4772-4779 .
Authors: Amita ;Mittal S.;Ganguly U.
DOI 10.1109/TED.2018.2870282
8 8

Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and beyond

Open Access
Conference Paper
Year: 2018. Volume: 2018-December , Pages: 35.6.1-35.6.4 .
Authors: Miyashita T.;Sun S.;Mittal S.;Kim M.S.;Pal A.;Sachid A.;Pathak K.;Cogorno M.;Kim N.S.
DOI 10.1109/IEDM.2018.8614487
3 4