Ministry of Education
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Dr Sukarn Agarwal

vidwan id: 215305
Male

Assistant Professor, Department of Computer Science and Engineering
Indian Institute of Technology (BHU), Varanasi

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Expertise

  • Computer Science Information Systems

Publications

Total Articles 25
Books 0
Proceedings 0

Publications

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Scopus

Citations 120
h-index 7

CrossRef

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Citations 28
h-index 3
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Professional Recognition

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Community & Membership

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Bio

Memory Architectures, Network on Chip Design, Thermal Aware Chip Management

Personal Details

  • Male
  • Assistant Professor , Indian Institute of Technology (BHU), Varanasi
  • Indian Institute of Technology (Banaras Hindu University)
PhD
Other Institute 2020
Assistant Professor Dec 2020 – Present
Indian Institute of Technology (BHU), Varanasi | Department of Computer Science and Engineering

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Co-Authors (5)

Ashwini

Ms Ashwini Kulkarni

COEP Technological University (formerly College of Engineering, Pune)

Hemangee K.

Prof Hemangee K. Kapoor

Indian Institute of Technology Guwahati

Rahul

Dr Rahul Gangopadhyay

Indian Institute of Technology (Indian School of Mines), Dhanbad

Soham Sundar

Prof Soham Sundar Chakraborty

Indian Institute of Technology Delhi

Shrinivas

Dr Shrinivas Mahajan

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Scholarly Work

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Scholarly Publications

Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets

Open Access
Conference Paper
Year: 2018. Volume: 2018-January , Pages: 457-458 .
Authors: Priya S.;Agarwal S.;Kapoor H.K.
DOI 10.1109/VLSID.2018.111
11

Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors

Open Access
Conference Paper
Year: 2018. Pages: 230-235 .
Authors: Kulkarni A.;Joshi C.;Rani K.;Agarwal S.;Mahajan S.P.;Kapoor H.K.
DOI 10.1109/ISED.2018.8704045

Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon

Open Access
Conference Paper
Year: 2018. Pages: 74-79 .
Authors: Rani K.;Agarwal S.;Kapoor H.
DOI 10.1109/ISED.2018.8704027
2

Towards analysing the effect of hybrid caches on the temperature of tiled chip multi-processors

Open Access
Conference Paper
Year: 2018. Pages: 52-57 .
Authors: Kulkarni A.;Rani K.;Agarwal S.;Mahajan S.P.;Kapoor H.K.
DOI 10.1109/iSES.2018.00021
3

Reuse-distance-aware write-intensity prediction of dataless entries for energy-efficient hybrid caches

Open Access
Article
Year: 2018. Volume: 26 , Issue: 10 , Pages: 1881-1894 .
Authors: Agarwal S.;Kapoor H.
DOI 10.1109/TVLSI.2018.2836156
14

Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors

Open Access
Conference Paper
Year: 2017. Pages: 29-34 .
Authors: Agarwal S.;Kapoor H.K.
DOI 10.1109/VLSID.2017.4
10

Towards a dynamic associativity enabled write prediction based hybrid cache

Open Access
Conference Paper
Year: 2017.
Authors: Agarwal S.;Kapoor H.K.
DOI 10.1109/ISVDAT.2016.8064870
1

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

Open Access
Conference Paper
Year: 2017.
Authors: Agarwal S.;Kapoor H.K.
DOI 10.1109/VLSI-SoC.2017.8203453
12