Ministry of Education
Vidvan Image

Prof Priyadarsan Patra

vidwan id: 198857
Male

Vice Chancellor,
Nist University

Orchid Icon 0000-0002-9585-0598 Google Scholar Icon 35577890000 Researcher Icon HPF-4591-2023 Google Scholar Icon _7U1pRMAAAAJ

Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 124
Books 0
Proceedings 0

Publications

No publication activity to display at the moment.

Scopus

Citations 408
h-index 11

CrossRef

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Citations 224
h-index 7
Google Scholar

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Professional Recognition

2009

ACM Senior Member

Association of Computing Machinery
2005

IEEE Senior Member

IEEE
1999

Distinguished Young Oriya Award

The Odisha Society of the Americas
1988

MCD Fellow

University of Texas at Austin
1993

CERC Scholar

ECE Dept.
1994

Scholarship

Oxford University Computing Lab
2010

Intel Hero (USA)

Intel Corp.
1997

Division Recongnition Award

Intel Corp.
2021

Fellow

Institution of Engineers

Community & Membership

2006

IEEE Oregon Section

Vice Chairperson
2008

National Science Foundation

USA
2016

IEEE CEDA

Executive Committee Member
2017

IEEE Comsoc

Executive Committee Member
2016

IEEE SVDTC

Founding Chair/President
2010

International Sysmposium on embedded System Design

Steering Committee Chair
2021

Silizium Circuits

IIT-Hyd
2019

Academic Council of XIM University

Member
2021

UPES Board of Management and Academic Council

Member
2020

Asian Institute of Public Health University

Advisor to the Board
2018

Chandler Unified School District

Encore Fellow
2011

Global Semiconductor Research Corp.

Member

DACS-2024 (International Conference on Data Analytics and Cyber Security) --- IIM Bodh Gay

2024
Invited Member

VLSI Professional Group

2023
Invited Member

IInstitution of Electronics and Telecommunication Engineers

2022
Fellow

Institute of Engineers

2021
Fellow

ACM

2005
Regular

IEEE

2000
Regular

Bio

As a scientist, technologist, professor and chief architect over 25+ years in creating and leading world-class research and development to support Server, tablet/phone SoC and Client processor architectures for power-performance optimized designs, and their Validation, Debug, and Test for several generations of flagship silicon devices/platforms – and educating on AI/ML/DL techniques/applications. My research interests include Applications of Machine Learning, Big Data & Cloud Computing, and

Personal Details

  • Male
  • Vice Chancellor , Nist University
  • Berhampur, Odisha, India
Ph.D.
The University of Texas at Austin 1995
M.S.
Other Institute 1985
B. Engg.
Other Institute 1983
Vice Chancellor Sep 2024 – Present
Nist University
Distinguished Professor Oct 2021 – Dec 2022
DIT University
Pro Vice Chancellor Oct 2021 – Sep 2024
DIT University
Dean Jan 2021 – Oct 2021
University of Petroleum and Energy Studies, Dehradun | Department of Computer Science and Engineering
Dean Jan 2019 – Jan 2021
Xavier University Bhubaneswar
Professor Jan 2019 – Sep 2020
XIM University, Bhubaneswar
Chief Scientist May 2016 – Mar 2018
Intel Labs
Principal Scientist Apr 2002 – May 2009
Intel Labs
Senior Scientist Sep 1995 – Mar 2002
Intel Labs
Research Associate May 1993 – Aug 1995
The University of Texas at Austin
Teaching Associate May 1990 – Jul 1993
The University of Texas at Austin

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Co-Authors (46)

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Prof Ashwini Vaidya

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Prof Venkata Krishna P

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Dr Hafizur Rahaman

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Dr Rajendra Baikady

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Dr Rajib Kar

National Institute of Technology Durgapur

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Prof Rakesh Kumar Bajaj

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Scholarly Work

AI Model and System for Mall Shop Front Detection and Classification in Realtime

Funding Agency: RaSpect AI

Primary Investigator

625,500

2021 - Ongoing

Ongoing
Early Design Exploration

Funding Agency: Intel Corp.

PI for internal support

1,000,000

2005 - 2007

Completed
Digital Transofrmation of Education for faculty and students

Funding Agency: Coursera in-kind grant

2,000,000

-0001 - Ongoing

Ongoing
Vision Processing using Nvidia GPU

Funding Agency: Nvidia Corp (Academic Ambassador grant)

2,000,000

-0001 - Ongoing

Ongoing

Transistor-level Optimization of VLSI Circuits

University University of Minnesota
Year 2002

Physical Design Techniques

University Iowa State University
Year 2006

Runtime Validation for Concurrent Processors

University Princeton University
Year 2009

Efficient observability enhancement techniques for post-silicon Validation and debug

University Univ of Florida
Year 2012

Portfolio Optimization

University Xavier Institute of Management
Year 2020

Academic Excellence Information System for Students

Priyadarsan Patra
Engineering and Technology Application No. : 15988/2022-CO/SW Filed : 26-07-2022
Published : N/A Filed

Academic Excellence Information System (AEIS) for Higher Education

Priyadarsan Patra
Engineering and Technology Application No. : 15987/2022-CO/SW Filed : 26-07-2022
Published : N/A Filed

Test, Verification, And Program And Method Of Debug Architecture

MARK B TROBOUGH;;KESHAVAN K TIRUVALLUR;;CHINNA B PRUDVI;;CHRISTIAN E LOVIN;;DAVID W GRAWROCK;;JAY J NEJEDLO;;ASHOK N KABADI;;TRAVIS K GOFF;;EVAN J HALPRIN;;KAPILA B UDAWATTA;;JIUN LONG FOO;;CHEAH WEE HOO;;VUI YONG LIEW;;SELVAKUMAR RAJA GOPAL;;YEN TAT LEE;;SAMIE B SAMAAN;;KIP C KILLPACK;;NIEL DOBLER;;NAGIB Z HAKIM;;BRIAN MEYER;;WILLIAM H PENNER;;JOHN L BAUDREXL;;RUSSELL J WUNDERLICH;;JAMES J GREALISH;;KYLE MARKLEY;;TIMOTHY S STOREY;;LOREN J MCCONNELL;;LYLE E COOL;;MUKESH KATARIA;;RAHIMA K MOHAMMED;;TIEYU ZHENG;;YI AMY XIA;;RIDVAN A SAHAN;;ARUN R RAMADORAI;;PRIYADARSAN PATRA;;EDWIN E PARKS;;ABHIJIT DAVARE;;PADMAKUMAR GOPAL;;BRUCE QUERBACH;;HERMAN W GERTLER;;KEITH DRESCHER;;SANJAY S SALEM;;DAVID C FLORY
Engineering and Technology Patent No. : JP 2017076412 A Filed : 21-11-2016
Published : 20-04-2017 Published

Program And Method Of Test, Verify And Debug Architecture

MARK B TROBOUGH;;KESHAVAN K TIRUVALLUR;;CHINNA B PRUDVI;;CHRISTIAN E LOVIN;;DAVID W GRAWROCK;;JAY J NEJEDLO;;ASHOK N KABADI;;TRAVIS K GOFF;;EVAN J HALPRIN;;KAPILA B UDAWATTA;;JIUN LONG FOO;;CHEAH WEE HOO;;VUI YONG LIEW;;SELVAKUMAR RAJA GOPAL;;YEN TAT LEE;;SAMIE B SAMAAN;;KIP C KILLPACK;;NIEL DOBLER;;NAGIB Z HAKIM;;BRIAN MEYER;;WILLIAM H PENNER;;JOHN L BAUDREXL;;RUSSELL J WUNDERLICH;;JAMES J GREALISH;;KYLE MARKLEY;;TIMOTHY S STOREY;;LOREN J MCCONNELL;;LYLE E COOL;;MUKESH KATARIA;;RAHIMA K MOHAMMED;;TIEYU ZHENG;;YI AMY XIA;;RIDVAN A SAHAN;;ARUN R RAMADORAI;;PRIYADARSAN PATRA;;EDWIN E PARKS;;ABHIJIT DAVARE;;PADMAKUMAR GOPAL;;BRUCE QUERBACH;;HERMAN W GERTLER;;KEITH DRESCHER;;SANJAY S SALEM;;DAVID C FLORY
Engineering and Technology Patent No. : JP 2014170576 A Filed : 28-04-2014
Published : 18-09-2014 Published

Test, Validation, And Debug Architecture

TROBOUGH MARK B;;TIRUVALLUR KESHAVAN K;;PRUDVI CHINNA B;;IOVIN CHRISTIAN E;;GRAWROCK DAVID W;;NEJEDLO JAY J;;KABADI ASHOK N;;GOFF TRAVIS K;;HALPRIN EVAN J;;UDAWATTA KAPILA B;;FOO JIUN LONG;;CHEAH WEE HOO;;LIEW VUI YONG;;GOPAL SELVAKUMAR RAJA;;LEE YUEN TAT;;SAMAAN SAMIE B;;KILLPACK KIP C;;DOBLER NEIL;;HAKIM NAGIB Z;;MEYER BRIAR;;PENNER WILLIAM H;;BAUDREXL JOHN L;;WUNDERLICH RUSSELL J;;GREALISH JAMES J;;MARKLEY KYLE;;STOREY TIMOTHY S;;MCCONNELL LOREN J;;COOL LYLE E;;KATARIA MUKESH;;MOHAMMED RAHIMA K;;ZHENG TIEYU;;XIA YI AMY;;SAHAN RIDVAN A;;RAMADORAI ARUN R;;PATRA PRIYADARSAN;;PARKS EDWIN E;;DAVARE ABHIJIT;;GOPAL PADMAKUMAR;;QUERBACH BRUCE;;GARTLER HERMANN W;;DRESCHER KEITH;;SALEM SANJAY S;;FLOREY DAVID C
Engineering and Technology Patent No. : US 2015/0127983 A1 Filed : 23-12-2010
Published : 05-07-2015 Published

Test, Validation, And Debug Architecture

TROBOUGH MARK B;;TIRUVALLUR KESHAVAN K;;PRUDVI CHINNA B;;IOVIN CHRISTIAN E;;GRAWROCK DAVID W;;NEJEDLO JAY J;;KABADI ASHOK N;;GOFF TRAVIS K;;HALPRIN EVAN J;;UDAWATTA KAPILA B;;FOO JIUN LONG;;CHEAH WEE HOO;;LIEW VUI YONG;;GOPAL SELVAKUMAR RAJA;;LEE YUEN TAT;;SAMAAN SAMIE B;;KILLPACK KIP C;;DOBLER NEIL;;HAKIM NAGIB Z;;MEYER BRIAN;;PENNER WILLIAM H;;BAUDREXL JOHN L;;WUNDERLICH RUSSELL J;;GREALISH JAMES J;;MARKLEY KYLE;;STOREY TIMOTHY S;;MCCONNELL LOREN J;;COOL LYLE E;;KATARIA MUKESH;;MOHAMMED RAHIMA K;;ZHENG TIEYU;;XIA YI AMY;;SAHAN RIDVAN A;;RAMADORAI ARUN R;;PATRA PRIYADARSAN;;PARKS EDWIN E;;DAVARE ABHIJIT;;GOPAL PADMAKUMAR;;QUERBACH BRUCE;;GARTLER HERMANN W;;DRESCHER KEITH;;SALEM SANJAY S;;FLOREY DAVID C
Engineering and Technology Patent No. : US10198333B2 Filed : 23-12-2010
Published : 05-02-2019 Granted

Test, Validation, And Debug Architecture

MARK B TROBOUGH;;KESHAVAN K TIRUVALLUR;;CHINNA B PRUDVI;;CHRISTIAN E IOVIN;;DAVID W GRAWROCK;;JAY NEJEDLO;;ASHOK KABADI;;TRAVIS K GOFF;;EVAN J HALPRIN;;KAPILA B UDAWATTA;;JIUN LONG FOO;;WEE HOO CHEAH;;VUI YONG LIEW;;SELVAKUMAR RAJA GOPAL;;YUEN TAT LEE;;SAMIE B SAMAAN;;KIP KILLPACK;;NEIL DOBLER;;NAGIB Z HAKIM;;BRIAN MEYER;;WILLIAM H PENNER;;JOHN BAUDREXL;;RUSSELL J WUNDERLICH;;JAMES GREALISH;;KYLE MARKLEY;;TIMOTHY S STOREY;;LOREN J MCCONNELL;;LYLE COOL;;MUKESH KATARIA;;RAHIMA MOHAMMED;;TIEYU ZHENG;;YI AMY XIA;;RIDVAN SAHAN;;ARUN R RAMADORAI;;PRIYADARSAN PATRA;;EDWIN E PARKS;;ABHIJIT DAVARE;;PADMAKUMAR GOPAL;;BRUCE QUERBACH;;HERMANN W GARTLER;;KEITH DRESCHER;;SANJAY S SALEM;;DAVID C FLOREY
Engineering and Technology Patent No. : GB 2493793B Filed : 23-12-2010
Published : 08-07-2020 Granted

Method And Device For Dynamically Verifying A Processor Architecture

PATRA PRIYADARSAN
Engineering and Technology Patent No. : US 2009/0248781 A1 Filed : 28-03-2008
Published : 01-10-2009 Published

Method And Device For Dynamically Verifying A Processor Architecture

PATRA PRIYADARSAN
Engineering and Technology Patent No. : US8055697B2 Filed : 28-03-2008
Published : 11-08-2011 Granted

Method And System For Validating A Processor In A Semiconductor Assembly

PATRA PRIYADARSAN
- Patent No. : US 2009/0240454 A1 Filed : 24-03-2008
Published : 24-09-2009 Published

Spatial Curvature For Multiple Objective Routing

PATRA PRIYADARSAN
Engineering and Technology Patent No. : US 2008/0115099 A1 Filed : 15-11-2006
Published : 15-05-2008 Published

Time Synthesis For Power Optimization Of High Performance Circuits

PATRA PRIYADARSAN;;CHAPPELL BARBARA
Engineering and Technology Patent No. : US 2004/0060016 A1 Filed : 22-09-2003
Published : 25-03-2004 Published

Noise And Power Optimization In High Performance Circuits

PATRA PRIYADARSAN;;CHAPPELL BARBARA
Engineering and Technology Patent No. : US 6721924 B2 Filed : 28-09-2001
Published : 13-04-2004 Granted

Time Synthesis For Power Optimization Of High Performance Circuits

PATRA PRIYADARSAN;;CHAPPELL BARBARA
Engineering and Technology Patent No. : US2003/0066037 A1 Filed : 28-09-2001
Published : 03-04-2003 Published

Method For Reducing Network Costs And Its Application To Domino Circuits

PATRA PRIYADARSAN
Engineering and Technology Patent No. : US 6556962 B1 Filed : 07-02-1999
Published : 29-04-2003 Granted

Power Consumption Reduction For Domino Circuits

PATRA PRIYADARSAN;;NARAYANAN UNNI K
Engineering and Technology Patent No. : US 6529861 B1 Filed : 07-02-1999
Published : 04-03-2003 Granted

Scholarly Publications

Message from the Organizing Chairs

Open Access
Editorial
Year: 2025. Pages: iii .
Authors: Sarveswaran K.;Vaidya A.;Bal B.K.;Shams S.;Thapa S.

Introduction

Open Access
Book Chapter
Year: 2024. Pages: 1-7 .
Authors: Datta A.;Jojo B.
DOI 10.4324/9781003311751-1

Message by Program Chair

Open Access
conference-paper
Year: 2023.
Authors:

Artificial Intelligence Driven Circuits and Systems

Open Access
book
Year: 2022.
Authors:

The Internet of Medical Things: Enabling Technologies and Emerging Applications

Open Access
book
Year: 2021.
Authors:

Test, validation, and debug architecture

Open Access
patent
Year: 2020.
Authors:

Enabling Hardware Performance Counters for Microkernel-Based Virtualization on Embedded Systems

Open Access
Article
IEEE Access. Year: 2020. Volume: 8 , Pages: 110550-110564 .
Authors: Mathew D.;Jose B.A.;Mathew J.;Patra P.
DOI 10.1109/ACCESS.2020.3002106
3 6

A course recommendation system based on grades

Open Access
Conference Paper
Year: 2020.
Authors: Mondal B.;Patra O.;Mishra S.;Patra P.
DOI 10.1109/ICCSEA49143.2020.9132845
4 47