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Dr D. Ajitha

vidwan id: 193347
Female

Associate Professor, Department of Software Systems
Vellore Institute of Technology, Vellore

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 9
Books 0
Proceedings 0

Publications

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Scopus

Citations 66
h-index 1

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Professional Recognition

2015

BEST Paper

SCoRED conference, Kuala Lumpur
2021

BEST Paper of the session

Secured Best Paper award of the session titled Design of Area Efficient Shift Register and Scan Flip
2021

BEST Paper

Secured Best Paper award for the paper entitled RT-Gate: Concept of Micro Level Polarization in QCA,
2021

Best faculty in ECE

Best faculty in ECE from Ambitions career council awards in 2021.
2020

BEST Paper

AESPCOM2020
2020

Third Prize

5G hackathon

Community & Membership

2020

Research and development cell, SNIST

Associate Dean
2018

ECE department, SITAMS

Question Paper setter

ISTE

2009
Lifetime

IETE

2009
AMIETE

Bio

D. Ajitha received a Bachelor of Technology degree from JNTU, Hyderabad in 2006 and M.Tech in VLSI System Design from JNTUA, Ananthapuramu in 2009. She obtained her Ph.D. degree from the Department of Electronics and Communication Engineering, JNTUCEA, Ananthapuramu, India. She is having lifetime professional memberships in IETE and ISTE. She has published 21 papers in International Conferences and Journals. Her area of research interest is Digital logic circuits in the nano field, Low power VLS

Personal Details

  • Female
  • Associate Professor , Vellore Institute of Technology, Vellore
  • Vellore, Tamil Nadu, India
Ph.D
Other Institute 2017
M.Tech
Sreenivasa Institute of Technology and Management Studies 2009
B.Tech
Other Institute 2006
Associate Professor May 2022 – Present
Vellore Institute of Technology, Vellore | Department of Software Systems
Associate Professor Mar 2017 – Apr 2022
Sreenidhi Institute of Science and Technology
Assistant Professor Sep 2009 – Feb 2017
Sreenivasa Institute of Technology and Management Studies | Ece

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Co-Authors (5)

Balwinder

Dr Balwinder Raj

National Institute of Technical Teachers Training & Research, Chandigarh

Nehru

Dr Nehru K

Madanapalle Institute of Technology & Science, Madanapalle

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Dr Nagarjuna Telagam

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Dr B R Ambedkar National Institute of Technology, Jalandhar

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Prof Sumalatha V

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Scholarly Work

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ASPT- IDENTIFYING PAPER CURRENCY: AUTOMATIC IDENTIFYING PAPER CURRENCY, STOCKS, STAMPS USING IMAGE PROCESSING TECHNOLOGY

Dr. P. V. N. REDDY
Dr. CHUKKA SANTHAIAH
M CHANDRA SEKHAR REDDY and Dr. D. A JITHA
Engineering and Technology Application No. : 202041030474 Filed : 17-07-2020
Published : N/A Published

Bit Synchronizer for BiPhase input with variable bitrate

Sreenidhi Institute of Science and technology
Engineering and Technology Application No. : 201941023850A Filed : 10-06-2019
Published : 09-08-2019 Filed

Scholarly Publications

Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register

Open Access
Article

A critical review of design and fabrication challenges in InP HEMTs for future terahertz frequency applications.

Open Access
article
Authors: D. Ajitha

Implementation of 40 GHz high-resolution set based VCRO for ISM band applications

Open Access
article

Fredkin gate based energy efficient reversible D flip flop design in quantum dot cellular automata. Materials Today:

Open Access
article
Authors: D. Ajitha

"2: 1 MUX Implementation Using NMV-Gate: NON MAJORITY GATE in QCA.

Open Access
book chapter
Authors: D. Ajitha

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

Open Access
Article
Authors: D. Ajitha, K. Venkata Ramanaiah, V. Sumalatha

AN EFFICIENT DESIGN OF XOR GATE AND ITS APPLICATIONS USING QCA

Open Access
article
Authors: D. Ajitha

Hybrid single-digit BCD adder using Quantum-dot Cellular Automata

Open Access
Conference Paper
Authors: D. Ajitha , K. Venkata Ramanaiah, V. Sumalatha
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