Ministry of Education
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Mr Ravi Siddhan

vidwan id: 191448
Male

Associate Professor,
Vellore Institute of Technology, Vellore

Orchid Icon 0000-0002-3266-2282 Google Scholar Icon 55764511700 Researcher Icon I-4195-2016 Google Scholar Icon SIp-BCMAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 20
Books 0
Proceedings 0

Publications

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Scopus

Citations 63
h-index 4

CrossRef

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Citations 12
h-index 2
Google Scholar

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Professional Recognition

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Community & Membership

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Bio

VLSI Design, ASIC DESIGN, Digital IC Design and Low Power VLSI design

Personal Details

  • Male
  • Associate Professor , Vellore Institute of Technology, Vellore
  • Vellore Institute of Technology
PhD
Other Institute 2020
Associate Professor Jan 2008 – Present
Vellore Institute of Technology, Vellore

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Co-Authors (6)

JAGADEESH

Dr JAGADEESH P

R M D Engineering College

Harish

Dr Harish Kittur

Vellore Institute of Technology, Vellore

Narendiran

Dr Narendiran S

Sri Krishna College of Technology, Coimbatore

Nithin

Dr Nithin M

R V College of Engineering, Bangalore

Marimuthu

Dr Marimuthu R

Vellore Institute of Technology, Vellore

Balamurugan

Dr Balamurugan S

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Scholarly Work

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Scholarly Publications

High Performance Clock Path elements for Clock Skew reduction

Open Access
Conference Paper
Year: 2019. Pages: 1663-1670 .
Authors: Ravi S.;Trehan S.;Jain M.;Kittur H.M.
DOI 10.1109/ICICICT46008.2019.8993375

Design and Analysis of an efficient 3D - Network on - Chip (NoC) Router

Open Access
Conference Paper
Year: 2018. Pages: 1857-1862 .
Authors: Veadesh B.;Ravi S.;Venkatapragadeesh B.
DOI 10.1109/ICRIEECE44171.2018.9009362

Power optimization techniques and physical design flow on repeaters for high-speed processor core in sub 14nm

Open Access
Conference Paper
Year: 2018. Pages: 424-428 .
Authors: Ravali K.;Ravi S.;Kittur H.M.
DOI 10.1109/RTEICT42901.2018.9012129

Design of high performance double precision hybrid ALU for SoC applications

Open Access
Conference Paper
Year: 2017. Volume: 2017-January , Pages: 1-6 .
Authors: Ravi S.;Adig ;Kittur H.M.
DOI 10.1109/ICMDCS.2017.8211610
1

A relative comparison of finfet and tunnel fet at 20 nm and study the performance of clock buffers and inverters using finfet

Open Access
Conference Paper
Year: 2017. Pages: 575-580 .
Authors: Ravi S.;Mandal S.;Baskar B.;Kittur H.M.
DOI 10.1201/9781315364094-103
1 1

Low power obstacle and skew aware clock tree synthesis

Open Access
Conference Paper
Year: 2017. Pages: 593-597 .
Authors: Ravi S.;Mittal Y.;Kittur H.M.
DOI 10.1201/9781315364094-106

Study the characteristics of the tunnel FET at 20 nm and explore the performance of clock buffers and inverters using tunnel FET

Open Access
Conference Paper
Year: 2017. Volume: 2017-December , Pages: 1-6 .
Authors: Mandal S.;Chatterjee S.;Ravi S.;Kittur H.M.
DOI 10.1109/ICEICE.2017.8191955

Design and analysis of clock gating elements

Open Access
Article
Indian Journal of Science and Technology. Year: 2016. Volume: 9 , Issue: 5 .
Authors: Ravi S.;Sinha S.;Adithyan R.;Kittur H.
DOI 10.17485/ijst/2016/v9i5/87184
3