Mr Ragunath Gopal

vidwan id: 191281

Male

Assistant Professor, School of Electronics Engineering
Vellore Institute of Technology, Vellore

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Expertise

Electrical and Electronic Engineering

Publications

Total Articles 7

Books 0

Proceedings 0

Publications

Scopus

Citations 2

h-index 1

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Citations 0

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Bio

law power and high arithmetic circuits in VLSI

Personal Details

Male
Assistant Professor , Vellore Institute of Technology, Vellore
Vellore Institute of Technology

PhD

Other Institute 2020

Assistant Professor Jul 2013 – Present

Vellore Institute of Technology, Vellore | School of Electronics Engineering

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Assistant Professor (Grade-I)

Dr N PRAKASH

Assistant Professor

Mr Mrinmoy Sadhukhan

Research Scholar

Mr Haranath Rakshit

Junior Research Fellow

Organisations (1349+)

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Dr Brindha K

Associate Professor

Dr Brisilla R M

Associate Professor

Dr Saravanan Balasubramanian

Associate Professor

Dr Selva Rani B

Associate Professor

Dr Budhaditya Bhattacharyya

Associate Professor

Dr Boominathan Perumal

Associate Professor

Dr Boopalan Ganapathy

Associate Professor

Mr Boopathi M

Assistant Professor

Dr Brijendra Singh

Associate Professor

Dr Brijesh Nair

Professor

Co-Authors (3)

Dr Elangovan Devaraj

Vellore Institute of Technology, Vellore

Dr Arunkumar Gopal

Vellore Institute of Technology, Vellore

Dr Sakthivel Ramachandran

Vellore Institute of Technology, Vellore

Scholarly Work

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Scholarly Publications

Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

Open Access

Article

Journal of Ambient Intelligence and Humanized Computing. Year: 2021. Volume: 12 , Issue: 5 , Pages: 5513-5524 .

Authors: Sakthivel R.;Ragunath G.

10.1007/s12652-020-02062-3

A high-speed BCD adder using single 4-bit binary adder and detector circuit

Open Access

Article

International Journal of Engineering and Advanced Technology. Year: 2019. Volume: 8 , Issue: 5 , Pages: 1994-1999 .

Authors: Ragunath G.;Sakthivel R.

Delay Optimized Binary to BCD Converter for Multi-operand Parallel Decimal Adder

Open Access

Conference Paper

Year: 2019.

Authors: Ragunath G.;Sugandh V.;Sakthivel R.

10.1109/ViTECoN.2019.8899475

Low Power Pre-Charge Free DCAM

Open Access

Conference Paper

Year: 2019.

Authors: Subba Rao Naidu Immadisetti C.V.;Ragunath G.

10.1109/ViTECoN.2019.8899390

An Area Efficient 16-bit Logarithmic Multiplier

Open Access

Conference Paper

Year: 2019.

Authors: Chaitanya M.B.K.;Sai Teja Y.;Teja K.R.;Ragunath G.

10.1109/ViTECoN.2019.8899395

Design and dSpace interfacing of current fed high gain dc to dc boost converter for low voltage applications

Open Access

Conference Paper

Year: 2017. Volume: 263 , Issue: 5 .

Authors: Mukhopadhyay D.;Das S.;Arunkumar G.;Elangovan D.;Ragunath G.

Low - power and area - efficient square - Root carry select adders using modified XOR gate

Open Access

Article

Indian Journal of Science and Technology. Year: 2016. Volume: 9 , Issue: 5 .

Authors: Ragunath G.;Sakthivel R.

10.17485/ijst/2016/v9i5/87181