Ministry of Education
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Dr Vanitha Mohanraj

vidwan id: 191175
Female

Associate Professor, School of Information Technology and Engineering
Vellore Institute of Technology, Vellore

Orchid Icon 0000-0001-7726-2621 Google Scholar Icon 57190578779 Researcher Icon U-7308-2019 Google Scholar Icon m9LPA3gAAAAJ

Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 40
Books 0
Proceedings 0

Publications

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Scopus

Citations 44
h-index 4

CrossRef

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Citations 10
h-index 2
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Professional Recognition

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Community & Membership

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Bio

High performance architectures for Cryptography algorithms, Machine Learning, IOT

Personal Details

  • Female
  • Associate Professor , Vellore Institute of Technology, Vellore
  • Vellore Institute of Technology
PhD
Other Institute 2016
Associate Professor Jun 2006 – Present
Vellore Institute of Technology, Vellore | School of Information Technology and Engineering

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Co-Authors (15)

Angulakshmi

Dr Angulakshmi Maruthamuthu

Vellore Institute of Technology, Vellore

Jasmine

Dr Jasmine Norman

Vellore Institute of Technology, Vellore

Sairabanu

Dr Sairabanu Jamal Mohammed

Vellore Institute of Technology, Vellore

Kishore

Dr Kishore Sanapala

Marri Educational Society's Marri Laxman Reddy Institute of Technology and Management

Harish

Dr Harish Kittur

Vellore Institute of Technology, Vellore

Deepa

Dr Deepa Mani

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Dr K Radhika

Muthayammal Engineering College

Mangayarkarasi

Dr Mangayarkarasi R

Vellore Institute of Technology, Vellore

Sakthivel

Dr Sakthivel Ramachandran

Vellore Institute of Technology, Vellore

Selvakumar

Dr Selvakumar R

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Subhashini

Dr Subhashini R

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Srinivasan

Dr Srinivasan Subha

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Tamil Priya

Ms Tamil Priya Dhandapani

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Vanmathi

Dr Vanmathi C

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Scholarly Work

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Scholarly Publications

Low leakage power Vedic multiplier using standard cell design

Open Access
Article
Indian Journal of Science and Technology. Year: 2015. Volume: 8 , Issue: 24 .
Authors: Sakthivel R.;Vanitha M.;Singh S.
DOI 10.17485/ijst/2015/v8i24/85349
1

CP-PLL design and implementation for mixed signal SOCS

Open Access
Article
Year: 2014. Volume: 9 , Issue: 23 , Pages: 20151-20160 .
Authors: Shravya K.V.;Kaur N.;Sakthivel R.;Vanitha M.

Low power high throughput reconfigurable stream cipher hardware VLSI architectures

Open Access
Article
International Journal of Information and Computer Security. Year: 2014. Volume: 6 , Issue: 1 , Pages: 1-11 .
Authors: Sakthivel R.;Vanitha M.;Kittur H.M.
DOI 10.1504/IJICS.2014.059785
1 4

Hardware and software implementation for highly secured Modified Wired Equivalent Privacy (MdWEP)

Open Access
Article
Year: 2013. Volume: 48 , Issue: 2 , Pages: 668-673 .
Authors: Vanitha M.;Selvakumar R.;Subha S.
1

Loop parallelization and pipelining implementation of AES algorithm using OpenMP and FPGA

Open Access
Conference Paper
Year: 2013. Pages: 481-485 .
Authors: Banu J.;Vanitha M.;Vaideeswaran J.;Subha S.
DOI 10.1109/ICE-CCN.2013.6528547
3 10

Low-power area efficient reconfigurable pipelined two's complement multiplier with reduced error

Open Access
Conference Paper
Year: 2012. Volume: 269 CCIS , Issue: PART I , Pages: 308-321 .
Authors: Sakthivel R.;Vanitha M.;Kittur H.
DOI 10.1007/978-3-642-29219-4_36

Highly secured high throughput VLSI architecture for AES algorithm

Open Access
Conference Paper
Year: 2012. Pages: 403-407 .
Authors: Vanitha M.;Sakthivel R.;Subha
DOI 10.1109/ICDCSyst.2012.6188751
2 9

Phase-locked loop with high stability against process variation and gain-boosting charge pump for current matching characteristics

Open Access
Article
Year: 2010. Volume: 46 , Issue: 3 , Pages: 431-442 .
Authors: Sujatha V.;Wahitha Banu R.S.D.;Sakthivel R.;Vanitha M.
2