Mr Jayakrishnan Pachaiappan

vidwan id: 190840

Male

Assistant Professor, School of Electronics Engineering
Vellore Institute of Technology, Vellore

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Expertise

Electrical and Electronic Engineering

Publications

Total Articles 24

Books 0

Proceedings 0

Publications

Scopus

Citations 67

h-index 4

CrossRef

Citations 34

h-index 3

Google Scholar

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Bio

Low power

Personal Details

Male
Assistant Professor , Vellore Institute of Technology, Vellore
Vellore Institute of Technology

PhD

Other Institute 2020

Assistant Professor Dec 2006 – Present

Vellore Institute of Technology, Vellore | School of Electronics Engineering

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Dr Brindha K

Associate Professor

Dr Brisilla R M

Associate Professor

Dr Saravanan Balasubramanian

Associate Professor

Dr Selva Rani B

Associate Professor

Dr Budhaditya Bhattacharyya

Associate Professor

Dr Boominathan Perumal

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Dr Boopalan Ganapathy

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Assistant Professor

Dr Brijendra Singh

Associate Professor

Dr Brijesh Nair

Professor

Co-Authors (3)

Dr Harish Kittur

Vellore Institute of Technology, Vellore

Dr Sivasankaran Kumaravel

Vellore Institute of Technology, Vellore

Mr Dhanabal Rengasamy

Vellore Institute of Technology, Vellore

Scholarly Work

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Scholarly Publications

Pipelined architecture for vedic multiplier

Open Access

Conference Paper

Year: 2014.

Authors: Harish Babu N.;Satish Reddy N.;Devendra B.;Jayakrishanan P.

10.1109/ICAEE.2014.6838437

Design and implementation of low power floating point arithmetic unit

Open Access

Article

Year: 2014. Volume: 9 , Issue: 3 , Pages: 339-346 .

Authors: Kukati S.;Sujana D.V.;Udaykumar S.;Jayakrishnan P.;Dhanabal R.

Implementation of non-linear pipelined floating point adder

Open Access

Conference Paper

Year: 2013. Pages: 257-259 .

Authors: Dipu P.;Hampannavar N.;Jayakrishnan P.

10.1109/ICGCE.2013.6823440

Comparison of architectures of a coarse-grain reconfigurable multiply-accumulate unit

Open Access

Conference Paper

Year: 2013. Pages: 225-230 .

Authors: Bidhul C.B.;Hampannavar N.;Joseph S.;Jayakrishnan P.;Kumaravel S.

10.1109/ICGCE.2013.6823433

A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimation

Open Access

Conference Paper

Year: 2013.

Authors: Aarthi N.;Athishkarthic K.S.;Kumar N.M.;Jayakrishnan P.

10.1109/C2SPCA.2013.6749410

Implementation of pipelined booth encoded wallace tree multiplier architecture

Open Access

Conference Paper

Year: 2013. Pages: 199-204 .

Authors: Kshirsagar R.;Aishwarya E.;Vishwanath A.;Jayakrishnan P.

10.1109/ICGCE.2013.6823428

Implementation of adder structure with fast carry network for high speed processor

Open Access

Conference Paper

Year: 2013. Pages: 188-190 .

Authors: Anand N.;Joseph G.;Raj J.;Jayakrishnan P.

10.1109/ICGCE.2013.6823425

Implementation of single precision floating point multiplier using Karatsuba algorithm

Open Access

Conference Paper

Year: 2013. Pages: 254-256 .

Authors: Mehta A.;Bidhul C.;Joseph S.;Jayakrishnan P.

10.1109/ICGCE.2013.6823439

Showing 9 to 16 of 24 results