Ministry of Education
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Dr Arunachalam Venkatesan

vidwan id: 190773
Male

Associate Professor, School of Electronics Engineering
Vellore Institute of Technology, Vellore

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 13
Books 0
Proceedings 0

Publications

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Scopus

Citations 29
h-index 2

CrossRef

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Citations 12
h-index 2
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Bio

VLSI DSP, Computer Arithmetic and VLSI architectures for Deep learning and Infernce Engines

Personal Details

  • Male
  • Associate Professor , Vellore Institute of Technology, Vellore
  • Vellore Institute of Technology
PhD
Other Institute 2016
Associate Professor Jun 2004 – Present
Vellore Institute of Technology, Vellore | School of Electronics Engineering

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Scholarly Work

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Scholarly Publications

Analysis Design of Convolution Operator for High Speed and High Accuracy Convolutional Neural Network-Based Inference Engines

Open Access
Article
IEEE Transactions on Computers. Year: 2022. Volume: 71 , Issue: 2 , Pages: 390-396 .
Authors: Deepika S.;Arunachalam V.
DOI 10.1109/TC.2021.3051627

Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length

Open Access
Article
Circuits, Systems, and Signal Processing. Year: 2021. Volume: 40 , Issue: 4 , Pages: 1818-1831 .
Authors: Arunachalam V.;Joseph Raj A.N.;Deepika S.
DOI 10.1007/s00034-020-01557-w
1

Fusion of near-infrared and RGB images on a FPGA using high level synthesis tool

Open Access
Article
Year: 2021. Volume: 9 , Issue: 3 , Pages: 104-114 .
Authors: Raj A.N.J.;Murugappan M.;Arunachalam
DOI 10.36909/jer.v9i3A.9167

Memory efficient ASIC implementation of line hough transform

Open Access
Conference Paper
Year: 2018. Pages: 718-723 .
Authors: Pachkor K.V.;Arunachalam V.
DOI 10.1109/RTEICT42901.2018.9012298

Efficient dual-precision floating-point fused-multiply-add architecture

Open Access
Article
Microprocessors and Microsystems. Year: 2018. Volume: 57 , Pages: 23-31 .
Authors: Arunachalam V.;Joseph Raj A.N.;Hampannavar N.;Bidul C.B.
DOI 10.1016/j.micpro.2017.12.009
1 2

Power domain, physical aware scan chain allocation and reordering

Open Access
Article
Indian Journal of Science and Technology. Year: 2016. Volume: 9 , Issue: 37 .
Authors: Divakar D.;Arunachalam V.
DOI 10.17485/ijst/2016/v9i37/102139

Design of 8 × 8 2D-DCT processor for high accuracy high performance applications

Open Access
Article
Year: 2015. Volume: 15 , Issue: 2 , Pages: 151-170 .
Authors: Arunachalam V.;Raj A.
DOI 10.17654/FJECDec2015_151_170

Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing application

Open Access
Article
Year: 2014. Volume: 8 , Issue: 6 , Pages: 526-531 .
Authors: Arunachalam V.;Joseph Raj A.N.
DOI 10.1049/iet-cds.2013.0457
9 21