Ministry of Education
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Manju Padidela

vidwan id: 179534
Female

Assistant Professor, Department of Electronics and Communication Engineering
BVRIT Hyderabad College of Engineering for Women

Orchid Icon 0000-0002-4151-6957 Google Scholar Icon 57209473819 Google Scholar Icon 625lCY8AAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 13
Books 0
Proceedings 0

Publications

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Scopus

Citations 3
h-index 1

CrossRef

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Citations 0
h-index 0
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Professional Recognition

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Community & Membership

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IAENG

2019
251371

Bio

VLSI

Personal Details

  • Female
  • Assistant Professor , BVRIT Hyderabad College of Engineering for Women
  • Mallampet, Hyderabad, Telangana, India
Masters
Other Institute 2009
B Tech
Other Institute 2007
Assistant Professor Oct 2021 – Present
BVRIT Hyderabad College of Engineering for Women | Department of Electronics and Communication Engineering
Assistant Professor Jul 2019 – Oct 2021
Malla Reddy College of Engineering for women
Assistant Professor Jul 2014 – Jun 2017
Malla Reddy Engineering College for women | ECE
Assistant Professor Jul 2012 – May 2014
Lords Institute of Engineering & Technology
Assistant Professor Jul 2010 – Jun 2012
Joginpally B.R Engineering College

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Scholarly Work

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PERFORMANCE OF MULTICARRIER MODULATION TECHNIQUES WITH AND WITHOUT PROPOSED MELS CHANNEL ESTIMATION METHOD

Praveen Kumar Malik
Shaik Nilofer
Manju Padidela
Engineering and Technology Application No. : 202211040825 Filed : 17-07-2022
Published : 22-07-2022 Published

SUPPORT VECTOR MACHINE FOR SPEECH RECOGNITION

malla reddy college of engineering for women
Engineering and Technology Application No. : 202041026035 A Filed : 20-06-2020
Published : 03-07-2020 Published

Scholarly Publications

Design and implementation of parallel array multiplIer using high speed adders

Open Access
article
Year: 2020. Volume: 29 , Pages: 2912-2923 .
Authors: Manju P

Design and implementation of parallel array multipler using high speed adders

Open Access
Article
Year: 2020. Volume: 29 , Issue: 6 , Pages: 2912-2923 .
Authors: Manju P.;Mouni N.;Madhavi T.

Design of vedic multiplier using GDI method

Open Access
Article
Year: 2019. Volume: 7 , Issue: 6 , Pages: 227-229 .
Authors: Manju P.;Sreelakshmi P.B.;Madhavi T.
3

Design of a high speed hybrid transistor logic (HTL) based cryptography

Open Access
Article
Year: 2019. Volume: 28 , Issue: 14 , Pages: 181-190 .
Authors: Manju P.;Madhavi T.

Design and Comparison of various VLSI adders using GDI method

Open Access
conference proceedings
Year: 2019. Pages: 0454 .
Authors: Manju P

Design of A High Speed Hybrid Transistor Logic (HTL) Multiplier Using HTL Adder

Open Access
article
Year: 2019. Volume: 75 , Pages: 81 - 95 .
Authors: Manju P
DOI 10.21506/j.ponte.2019.11.7

Design of A High Speed Novel Adder Using Hybrid Transistor Logic

Open Access
article
Year: 2018. Volume: 10 , Pages: 04 special issue .
Authors: Manju P

Reversible Logic to Cryptographic Hardware using Montgomery Modular Multiplication Algorithm

Open Access
article
Year: 2017.
Authors: Manju P