Nagaleela Saikam

vidwan id: 178962

Female

Assistant Professor, Department of Electronics and Communication Engineering
Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology

0000-0003-3822-5072 Google Scholar Icon

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57159457100

Expertise

Electrical and Electronic Engineering

Publications

Total Articles 6

Books 0

Proceedings 0

Publications

Scopus

Citations 10

h-index 2

CrossRef

Citations 3

h-index 1

Google Scholar

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Professional Recognition

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Community & Membership

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ISTE

2015

life membership

Bio

Low power VLSI Design

Personal Details

Female
Assistant Professor , Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology
Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology

M.Tech.

Other Institute 2015

B.E.

Other Institute 2008

Assistant Professor Dec 2014 – Present

Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology | Department of Electronics and Communication Engineering

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Junior Research Fellow

Organisations (496+)

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Suneetha Bodduluri

Programmer

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Assistant Professor

Dr Baby Vadlana

Associate Professor

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Co-Authors (3)

Prof Yarlagadda Padma Sai

Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology

Dr Shanthi Ghanta

Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology

Prof Rajendra Prasad Somineni

Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology

Scholarly Work

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Scholarly Publications

Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology

Conference Paper

Authors: Shanthi G.;Sainath G.;Ashwini N.;Sai P.G.;Kumar P.A.;Leela S.N.

DOI

10.1109/INCET61516.2024.10593607

Design of Shift Registers Using DG-FinFET for Low Power Applications

Conference Paper

Year: 2024. Pages: 151-155 .

Authors: Shanthi G.;Naga Vaishnavi K.;Manasa N.;Surya Pramod V.;Naga Leela S.;Shoukath Vali S.

DOI

10.1109/ICDCS59278.2024.10560604

A Novel Design of High Speed Multiplier Using Hybrid Adder Technique

Conference Paper

Authors: Leela S.N.;Keerthi Chandrika D.;Swetha K.;Kalali D.G.;Shanthi G.

DOI

10.1109/INOCON60754.2024.10512237

Design of DADDA Multiplier Using High Performance and Low Power Full Adder

Conference Paper

Authors: Nagaleela S.;Shanthi G.;Manisha B.;Bharath P.;Praneeth E.

DOI

10.1109/ICCCNT56998.2023.10308152

3

Design of Wallace tree multiplier circuit using high performance and low power full adder

Conference Paper

E3S Web of Conferences. Year: 2023. Volume: 391 .

Authors: Naga Leela S.;Manisha B.;Bharath P.;Praneeth E.

DOI

10.1051/e3sconf/202339101025

1

Low leakage CNTFET full adders

Conference Paper

Year: 2015. Pages: 174-179 .

Authors: Rajendra Prasad Somineni,Y Padma sai,S Naga Leela

3

6