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Dr Shiraz Husain

vidwan id: 178765
Male

Assistant Professor, Department of Electrical and Electronics Engineering
Shri Vaishnav Vidyapeeth Vishwavidyalaya

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 14
Books 0
Proceedings 0

Publications

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Scopus

Citations 2
h-index 1

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Professional Recognition

2017

TBT Challange

E-yantra, IIT Bombay.
2022

Best Paper Award

6th Doctoral Conference, Shodh 2022, SVVV, Indore
2020

Dronacharya Award

Navarachanaa 2020
2003

President Students Council

Govt Polytechnic Khandwa
2020

Elite

NPTEL EXAMINATIONS
2023

Top 1% in Digital System Design

NPTEL Examinations Jan-April 2023

Community & Membership

2015

IRED

Associate Member
2018

Center of Excellence in Sustainable Development, SVVV, Indore

Member
2022

Journal of Supercomputing

Reviewer

IAENG

2022
Associate Member

ISTE

2016
Life Member

Bio

Area of Interest Includes Cmos Vlsi Design and Embedded System Design

Personal Details

  • Male
  • Assistant Professor , Shri Vaishnav Vidyapeeth Vishwavidyalaya
  • Shri Vaishnav Vidyapeeth Vishwavidyalaya, Ujjain Road
M.Tech
Other Institute 2014
B.Tech
Other Institute 2010
Diploma
Other Institute 2003
Assistant Professor Sep 2014 – Present
Shri Vaishnav Vidyapeeth Vishwavidyalaya | Department of Electrical and Electronics Engineering

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Co-Authors (2)

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Mr Preet Jain

Shri Vaishnav Vidyapeeth Vishwavidyalaya

Scholarly Work

LED Display

Funding Agency: SVVV Indore

Design and Implementation

38,000

2018 - 2018

Completed
Humanoid Robot

Funding Agency: SVVV Indore

Design and Implementation

90,000

2017 - 2018

Completed
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Scholarly Publications

Transforming Tomorrow: Innovative Solutions and Global Trends in Electrical and Electronics Engineering

Open Access
book
Authors: Dr. Namit Gupta, Dr. Anjali Gupta, Dr. Naresh Purohit, Dr. Shiraz Husain

Reliable Computing by Distributed Clocking Based Sequential Circuits in Quantum Dot Cellular Automata

Open Access
conference-paper
Authors:

Harnessing Fault Tolerant Capabilities of USE Clocking Scheme for Designing QCA Flip- flops

Open Access
Conference Paper
Authors: Husain S.;Gupta N.
1

Enhancing fault tolerance in QCA-based RAM cells: A USE clock-driven approach with a novel majority voter

Open Access
Article

Design of optimum fault tolerant decoder using five input majority voter based on quantum dot cellular automata

Open Access
Conference Paper

Real Hardware Lab on Web

Open Access
conference-paper
Authors:

Design of Fault Tolerant T Flip-flop Based On USE Clocking Scheme

Open Access
conference-paper
Authors:

A Review on Defect Characterization, Fault Tolerant Strategies and Clocking Mechanisms in Quantum Dot Cellular Automata

Open Access
conference-paper
Authors: