Ministry of Education
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Dr SAKTHIVEL PALANIAPPAN

vidwan id: 170057
Male

Professor, Electrical and Electronics Engineering
Velalar College of Engineering and Technology

Orchid Icon 0000-0003-0117-1007 Google Scholar Icon 57214368647

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 12
Books 0
Proceedings 0

Publications

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Scopus

Citations 9
h-index 2

CrossRef

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Citations 1
h-index 1
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Professional Recognition

2006

Best Teaching staff

Velalar College of Engineering and Technology
2010

First Rank in the Student Feed Back in the Average of Even semester of 2008-2009 and Odd semester of

Velalar College of Engineering and Technology
2013

Certificate of Appreciation for Campus Infrastructure

Velalar College of Engineering and Technology

Community & Membership

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The Institute of Electrical and Electronics Engineers(IEEE)

2020
Annual Type

Institution of Engineers(India)

2020
Life Member (FIE)

Indian Society of Systems for Science & Engineering

2015
Life Member

The Indian Society For Technical Education

2005
Life Member

Indian Society for Technical Education

2005
Life Member

Bio

Dr.P.Sakthivel, M.E., Ph.D. BE-EEE, ME- Applied Electronics (EEE), Ph.D- Electrical Engg. Professor and Head, Velalar College of Engineering and Technology, Erode - 638012.

Personal Details

  • Male
  • Professor , Velalar College of Engineering and Technology
  • Thindal
Ph.D
Anna University 2014
M.E.
Coimbatore Institute of Technology 2001
B.E.
Coimbatore Institute of Technology 1998
Professor Apr 2002 – Present
Velalar College of Engineering and Technology | Electrical and Electronics Engineering
Lecturer Mar 2001 – Apr 2002
Adhiyamaan College of Engineering | Electronics and Communication Engineering

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Organisations (27+)

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ARUN KUMAR

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Co-Authors (2)

Kalavathi Devi

Dr Kalavathi Devi T

Kongu Engineering College, Erode

Sathish Kumar

Dr Sathish Kumar S

M Kumarasamy College of Engineering, Karur

Scholarly Work

STTP on SOLAR ENERGY CONVERSION SYSTEMS : TECHNOLOGIES, DESIGN AND APPLICATIONS

Funding Agency: AICTE

Coordinator

2,93,000.00/-

2020 - Ongoing

Ongoing
AICTE- MODERNIZATION AND REMOVAL OF OBSOLESCENCE (MODROBS) TITLE : MODERNIZATION OF POWER ELECTRONICS LABORATORY

Funding Agency: AICTE

Coordinator

5,33,000.00/-

2019 - Ongoing

Ongoing
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Scholarly Publications

Analysis of Overloading in Trucks using Embedded Controller

Open Access
Conference Paper
Year: 2020. Pages: 944-949 .
Authors: Thangavel K.D.;Palaniappan S.;Chandrasekar G.;Muthusamy C.
DOI 10.1109/ICESC48915.2020.9155760
1

Performance analysis of vlsi architecture of viterbi decoder in wlan using the sleepy keeper technique

Open Access
Article
Year: 2020. Volume: 73 , Issue: 8 , Pages: 1123-1131 .
Authors: Thangavel K.D.;Palaniappan S.;Shanmugam S.K.
DOI 10.7546/CRABS.2020.08.11
1 2

Low power sleepy keeper technique based VLSI architecture of Viterbi decoder in WLANs

Open Access
Article
Australian Journal of Electrical and Electronics Engineering. Year: 2020. Volume: 17 , Issue: 4 , Pages: 263-268 .
Authors: Thangavel K.D.;Palaniappan S.
DOI 10.1080/1448837X.2020.1844366
2

A Design of Phase Locked loop Based Frequency Synthesizer using 4/5 Prescalar circuit

Open Access
other
International Journal of Engineering and Advanced Technology. Year: 2019. Volume: 8 , Pages: 581-586 .
Authors: T.Kalavathi Devi and P.Sakthivel

Monitoring and Analysis of Water Quality Parameters for Diagnosis of Safe Drinking Purpose using Wireless Sensor Network

Open Access
other
Year: 2019. Volume: 9 , Pages: 1478-1482 .
Authors: T. Kalavathi Devi and P.Sakthivel
DOI 10.35940/ijitee.B6658.129219

Design and FPGA implementation of bit level pipelined digit serial VLSI architecture for a viterbi decoder

Open Access
Article
Year: 2016. Volume: 15 , Issue: 7 , Pages: 1232-1242 .
Authors: Kalavathidevi T.;Sakthivel P.
DOI 10.3923/ajit.2016.1232.1242

Efficient Low Power Design of 4-Tap and 6-Tap 2d Daubechies Wavelet Filters using Pipelined Direct Mapping Method

Open Access
other
Asian Journal of Research in Social Sciences and Humanities. Year: 2016. Volume: 6 , Pages: 1453-1470 .
Authors: P.Sakthivel and T Kalavathi devi
DOI 10.5958/2249-7315.2016.00298.7

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Open Access
Article
Year: 2015. Volume: 2015 .
Authors: Devi T.K.;Palaniappan S.
DOI 10.1155/2015/621012
4