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Nagarathna R

vidwan id: 167937

Female

Assistant Professor, Department of Electronics and Telecommunication Engineering
Dayananda Sagar College of Engineering, BANGALORE

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Expertise

Telecommunications

Publications

Total Articles 7

Books 0

Proceedings 0

Publications

Scopus

Citations 9

h-index 2

CrossRef

Citations 6

h-index 2

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Professional Recognition

2024

Elite Gold and Topper

NPTEL

Community & Membership

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Bio

VLSI design and Embedded systems

Personal Details

Female
Assistant Professor , Dayananda Sagar College of Engineering, BANGALORE
Department of Electronics and Telecommunication Engineering, Dayananda College of Engineering

M.Tech

Other Institute 2009

Assistant Professor Aug 2009 – Present

Dayananda Sagar College of Engineering, BANGALORE | Department of Electronics and Telecommunication Engineering

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Co-Authors (9)

Dayananda Sagar College of Engineering, BANGALORE

Mr Chetan Umadi

Dayananda Sagar College of Engineering, BANGALORE

Dayananda Sagar College of Engineering, BANGALORE

Dr S P Meharunnisa Begum

Dayananda Sagar College of Engineering, BANGALORE

P.E.S. College of Engineering

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Dr Srividya B V

Dayananda Sagar College of Engineering, BANGALORE

M S Ramaiah Institute of Technology, Bangalore

Vidyavardhaka College of Engineering

Scholarly Work

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Heuristic Multi-valued Focal Plane Processor with Embedded Cryptosystem

Dayananda Sagar College of Engineering

- Application No. : 202441097947 Filed : 19-12-2024

Published : 20-12-2024 Published

Scholarly Publications

Low-Power VLSI Architecture for Ternary Galois Field

Article

Year: 2024. Volume: 11 , Issue: 3 , Pages: 113-135 .

Authors: Srividya B.V.;Nagarathna ;Aswatha A.R.

DOI

10.14445/23488379/IJEEE-V11I3P109

DESIGN AND PERFORMANCE ANALYSIS OF TERNARY LOGIC BASED ALU USING DOUBLE PRECISION FLOATING POINT

Article

Proceedings on Engineering Sciences. Year: 2024. Volume: 6 , Issue: 3 , Pages: 903-914 .

Authors: Nagarathna R.;Aswatha A.R.

DOI

10.24874/PES06.03.002

1

Low Latent Fixed Width Multiplier for Error Resilient Computation

Article

Year: 2024. Volume: 11 , Issue: 6 , Pages: 182-187 .

Authors: Srividya B.V.;Meharunnissa S.P.;Umadi C.;Nagarathna ;Kumar S.

DOI

10.14445/23488379/IJEEE-V11I6P120

A Brief Review on Multiple-Valued Logic-based Digital Circuits

conference-paper

Year: 2022. Volume: 248 , Pages: 329-337 .

Authors: Nagarathna;Jamuna, S.

3

3

Design and Development of a Smart Campus using Augmented Reality(SCAR)

conference-paper

Authors: Sundarramurthi, M.;Chandrashekar, K.;Nagarathna

2

An efficient high-throughput routing with successive interference cancellation in wireless sensor networks

Conference Paper

Year: 2017. Pages: 866-868 .

Authors: Tejaswini S.;Nagarathna

DOI

10.1109/RTEICT.2016.7807951

3

2

Implementation of low cost protocol converter using common media device

conference-paper

Year: 2017. Pages: 780-783 .

Authors: Ananda, M.P.;Nagarathna, R.;Krishna, L.;Rajeswari, P.

DOI

10.1109/ICIMIA.2017.7975572

1