Ministry of Education
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Dr Amit Jain

vidwan id: 162393
Male

Associate Professor, Department of Electronics and Communication Engineering
C M R Institute of Technology, BANGALORE

Orchid Icon 0000-0001-7809-6581 Google Scholar Icon 57199316641 Researcher Icon AAU-6639-2020 Google Scholar Icon uh_YWl8AAAAJ&view_op

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 43
Books 0
Proceedings 0

Publications

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Scopus

Citations 122
h-index 7

CrossRef

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Citations 123
h-index 6
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Professional Recognition

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Bio

VLSI Circuit Design, Nanodevices Modeling and Simulation

Personal Details

  • Male
  • Associate Professor , C M R Institute of Technology, BANGALORE
  • CMR Institute of Technology, 132 AECS Layout, ITPL Main Road, Kundalahalli
Ph.D
Jadavpur University 2017
Associate Professor Jul 2016 – Present
C M R Institute of Technology, BANGALORE | Department of Electronics and Communication Engineering

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Co-Authors (7)

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Dr Majid Zaman

University of Kashmir

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Prof Krishna Lal Baishnab

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Dr Khuraijam Nelson Singh

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Dr Priyanka Saha

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Prof Subir Kumar Sarkar

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Scholarly Work

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Scholarly Publications

Single electron threshold logic based Feynman gate implementation

Open Access
Conference Paper
Year: 2017. Pages: 266-268 .
Authors: Ghosh A.;Jain A.;Singh N.B.;Sarkar S.K.
DOI 10.1109/ICRCICN.2016.7813668
3 4

A nanoelectronic neuron cell for image processing application based on cellular neural/non-linear network architecture

Open Access
Article
Journal of Nanoelectronics and Optoelectronics. Year: 2016. Volume: 11 , Issue: 3 , Pages: 356-362 .
Authors: Jain A.;Ghosh A.;Singh N.B.;Sarkar S.K.
DOI 10.1166/jno.2016.1906
1 2

A modified macro model approach for SPICE based simulation of single electron transistor

Open Access
Article
Journal of Computational Electronics. Year: 2016. Volume: 15 , Issue: 2 , Pages: 400-406 .
Authors: Ghosh A.;Jain A.;Singh N.B.;Sarkar S.K.
DOI 10.1007/s10825-015-0790-1
16 17

Implementation Aspects of Logic Functions using Single Electron Threshold Logic Gates and Hybrid SET-MOS Circuits

Open Access
Article
IETE Journal of Research. Year: 2016. Volume: 62 , Issue: 4 , Pages: 479-487 .
Authors: Jain A.;Ghosh A.;Singh N.B.;Sarkar S.K.
DOI 10.1080/03772063.2015.1086703
2 1

Analytical modeling of read noise margin of a CNFET based 6T SRAM cell

Open Access
Article
Analog Integrated Circuits and Signal Processing. Year: 2015. Volume: 83 , Issue: 3 , Pages: 369-376 .
Authors: Saha P.;Jain A.;Sarkar S.K.
DOI 10.1007/s10470-015-0523-1
2 4

Design and implementation of SET-CMOS hybrid half subtractor

Open Access
Conference Paper
Year: 2015.
Authors: Ghosh A.;Jain A.;Singh N.B.;Sarkar S.K.
DOI 10.1109/INDICON.2014.7030405
8 8

A Comparative Study of Single Electron Threshold Logic-Based and SET-MOS Hybrid Based Half Subtractor

Open Access
Conference Paper
Year: 2015. Volume: 335 , Pages: 367-373 .
Authors: Arpita Ghosh ., Amit Jain ., N. Basanta Singh ., Subir Kumar Sarkar .,
DOI 10.1007/978-81-322-2274-3_40
2

A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits

Open Access
Article
Analog Integrated Circuits and Signal Processing. Year: 2015. Volume: 82 , Issue: 3 , Pages: 653-662 .
Authors: Jain A.;Ghosh A.;Singh N.B.;Sarkar S.K.
DOI 10.1007/s10470-015-0491-5
15 19