Ministry of Education
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Dr Saroja V Siddamal

vidwan id: 152355

Head of the School, Department of Electrical and Electronics Engineering
KLE Technological University

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 73
Books 0
Proceedings 0

Publications

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Scopus

Citations 154
h-index 7

CrossRef

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Citations 111
h-index 5
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Bio

Digital VLSI, VLSI testing and Verification, VLSI architecture design

Personal Details

  • Head of the School , KLE Technological University
  • KLE Technological University
Ph.D
Jawaharlal Nehru Technological University Hyderabad 2013
Head of the School Jul 2024 – Present
KLE Technological University | Department of Electrical and Electronics Engineering
Professor Oct 2002 – Jul 2024
KLE Technological University | School of Electronics and Communication Engineering

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Organisations (558+)

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Basavaraj

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Balachandra

Mr Balachandra Halemani

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Narasimha

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Arundati

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Arun Y.

Dr Arun Y. Patil

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Co-Authors (10)

R M

Dr R M Banakar

KLE Technological University

Dattaprasad

Dr Dattaprasad Annasaheb Torse

KLE Technological University

Jayashree

Jayashree Mallidu

KLE Technological University

Nalini C

Dr Nalini C Iyer

KLE Technological University

Sanjay

Dr Sanjay Kotabagi

KLE Technological University

Shraddha

Shraddha Hiremath

KLE Technological University

Suhas

Mr Suhas Shirol

KLE Technological University

Sujata

Dr Sujata Kotabagi

KLE Technological University

Suneeta

Dr Suneeta Budihal

KLE Technological University

Vijay

Dr Vijay H M

KLE Technological University

Scholarly Work

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Scholarly Publications

A survey on compressive sensing

Open Access
Conference Paper
Year: 2015. Pages: 639-643 .
Authors: Siddamal K.V.;Bhat S.P.;Saroja V.S.
DOI 10.1109/ECS.2015.7124986
4 9

High-Speed low-power VLSI architecture for SPST-equipped booth multiplier using modified carry look ahead adder

Open Access
Conference Paper
Year: 2014. Volume: 248 LNEE , Pages: 461-469 .
Authors: Mudhenagudi P.S.;Sugur N.V.;Siddamal S.V.;Banakar R.M.
DOI 10.1007/978-81-322-1157-0_47

Design and implementation of high throughput and area efficient hard decision viterbi decoder in 65nm technology

Open Access
Conference Paper
Year: 2014. Pages: 353-358 .
Authors: Sugur N.;Siddamal S.;Vemala S.
DOI 10.1109/VLSID.2014.67
1 4

Memory optimized design of reciprocal unit

Open Access
Conference Paper
Year: 2013. Volume: 174 AISC , Pages: 339-345 .
Authors: Nadaf M.M.;Banakar R.M.;Siddamal S.V.
DOI 10.1007/978-81-322-0740-5_40

High speed low power VLSI architecture for SPST adder using modified carry look ahead adder

Open Access
Conference Paper
Year: 2013. Volume: 174 AISC , Pages: 461-466 .
Authors: Narayan V.S.;Pratima S.M.;Saroja V.S.;Banakar R.M.
DOI 10.1007/978-81-322-0740-5_56
1 2

High speed signed multiplier for Digital Signal Processing applications

Open Access
Conference Paper
Year: 2012.
Authors: Saokar S.;Banakar R.;Siddamal S.
DOI 10.1109/ISPCC.2012.6224373
13 24

Timing consideration in synchronous system level design

Open Access
Conference Paper
Year: 2011. Pages: 532-534 .
Authors: Siddamal S.;Banakar R.;Jinaga B.
DOI 10.1109/ICCSP.2011.5739379

Split step method in the analysis and modeling of optical fiber communication system

Open Access
Conference Paper
Year: 2011. Volume: 125 CCIS , Pages: 254-261 .
Authors: Siddamal S.;Banakar R.;Jinaga B.
DOI 10.1007/978-3-642-18440-6_32
3 5