Ministry of Education
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Dr Vasantha M H

vidwan id: 141242
Male

Associate Professor, Department of Electronics and Communication Engineering
National Institute of Technology, Goa

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 82
Books 0
Proceedings 0

Publications

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Scopus

Citations 979
h-index 16

CrossRef

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Citations 211
h-index 6
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Professional Recognition

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Community & Membership

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IEEE

2022
Member

Bio

Low voltage, Low power analog mixed signal circuits, Continuous-time filter Circuits, System on Chip

Personal Details

  • Male
  • Associate Professor , National Institute of Technology, Goa
  • National Institute of Technology Goa
Ph.D
Other Institute 2014
Associate Professor Aug 2013 – Present
National Institute of Technology, Goa | Department of Electronics and Communication Engineering

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Co-Authors (11)

B. Naresh Kumar

Dr B. Naresh Kumar Reddy

National Institute of Technology Tiruchirappalli

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Dr Prashanth G R

National Institute of Technology, Goa

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Dr Ravi Prasad K J

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Scholarly Work

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NOC

University National Institute of Technology
Year 2018
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Scholarly Publications

A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique

Open Access
Conference Paper
Year: 2025.
Authors: Mestry S.;Siddharth R.K.;Nithin Kumar Y.B.;Vasantha M.H.;Bonizzoni E.
DOI 10.1109/ISCAS56072.2025.11043859

Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating Techniques

Open Access
Conference Paper
Year: 2024. Pages: 99-103 .
Authors: Kumar Y.A.;Nithin Kumar Y.B.;Vasantha M.H.;Siddharth R.K.
DOI 10.1109/iSES63344.2024.00030

Side Channel Attack on 8051 Microcontroller

Open Access
Conference Paper
Year: 2024. Pages: 354-359 .
Authors: Yuktha M.;Patel P.;Vasantha M.H.
DOI 10.1109/iSES63344.2024.00080

A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS

Open Access
Article
IEEE Transactions on Electron Devices. Year: 2024. Volume: 71 , Issue: 2 , Pages: 1054-1059 .
Authors: Dohar S.S.;Siddharth R.K.;Vasantha M.H.;Nithin Kumar Y.B.
DOI 10.1109/TED.2023.3343316
5

An Error Bound Particle Swarm Optimization for Analog Circuit Sizing

Open Access
Article
IEEE Access. Year: 2024. Volume: 12 , Pages: 50126-50136 .
Authors: Shreeharsha K.G.;Siddharth R.K.;Vasantha M.H.;Nithin Kumar Y.B.
DOI 10.1109/ACCESS.2024.3385491
1

N-Parallel Paths-Based D-Latch for High-Speed Applications

Open Access
Article
IEEE Access. Year: 2024. Volume: 12 , Pages: 162930-162938 .
Authors: Rakhi R.;Siddharth R.K.;Shreeharsha K.G.;Vasantha M.H.;Nithin Kumar Y.B.
DOI 10.1109/ACCESS.2024.3491577
1

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

Open Access
Conference Paper
Year: 2023. Volume: 2023-May .
Authors: Balaji R.;Siddharth R.K.;Naik S.;Kumar Y.B.N.;Vasantha M.H.;Bonizzoni E.
DOI 10.1109/ISCAS46773.2023.10181677
3

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

Open Access
Article
IEEE Access. Year: 2023. Volume: 11 , Pages: 123577-123588 .
Authors: Shreeharsha K.G.;Siddharth R.K.;Vasantha M.H.;Kumar Y.B.N.
DOI 10.1109/ACCESS.2023.3329698
6