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Dr Naveen Kadayinti

vidwan id: 128036
Male

Assistant Professor (Grade-I), Department of Electrical, Electronics and Communication Engineering
Indian Institute of Technology Dharwad

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 17
Books 0
Proceedings 0

Publications

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Scopus

Citations 43
h-index 4

CrossRef

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Citations 25
h-index 3
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Professional Recognition

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Bio

Wired and Wireless Communication Circuits and Mixed Signal SoC Design and Test

Personal Details

  • Male
  • Assistant Professor (Grade-I) , Indian Institute of Technology Dharwad
  • Indian Instutite of Technology Dharwad
PhD
Other Institute 2017
Assistant Professor (Grade-I) May 2018 – Present
Indian Institute of Technology Dharwad | Department of Electrical, Electronics and Communication Engineering

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Co-Authors (4)

Amitalok Jayant

Dr Amitalok Jayant Budkuley

Indian Institute of Technology Kharagpur

Maryam Shojaei

Dr Maryam Shojaei Baghini

Indian Institute of Technology Bombay

Ruma

Dr Ruma Ghosh

Indian Institute of Technology Dharwad

Seena

Dr Seena V

Indian Institute of Space Science and Technology

Scholarly Work

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Scholarly Publications

CMOS-MEMS Accelerometer with Stepped Suspended Gate FET Array: Design Analysis

Open Access
Article

Effect of jitter on the settling time of mesochronous clock retiming circuits

Open Access
Article

Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects

Open Access
Article

A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects

Open Access
Conference Paper
Authors: Kadayinti N.;Baghini M.S.;Sharma D.K.

Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter

Open Access
Conference Paper
Authors: Shirwaikar M.;Kadayinti N.;Sharma D.

Settling time of mesochronous clock re-timing circuits in the presence of timing jitter

Open Access
Conference Paper
Authors: Kadayinti N.;Budkuley A.;Sharma D.

Sense amplifier comparator with offset correction for decision feedback equalization based receivers

Open Access
Article

Testable design of repeaterless low swing on-chip interconnect

Open Access
Conference Paper
Authors: Naveen K.;Sharma D.K.
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