Dr Jitendra Kanungo

Male

Associate Professor, Department of Electronics and Communication Engineering
Jaypee University of Engeenering & Technology, Guna

0000-0003-3248-4997 Google Scholar Icon

55004327500 Researcher Icon

AAG-5952-2021 Google Scholar Icon

5gt65tgAAAAJ

Expertise

Electrical and Electronic Engineering

Publications

Total Articles 61

Books 0

Proceedings 0

Publications

Scopus

Citations 200

h-index 8

CrossRef

Citations 114

h-index 7

Google Scholar

Loading Scholar statistics...

Professional Recognition

No Data Found

There is currently nothing to display here.

Community & Membership

2020

IEEE Young Professional

Senior Member

IEEE

2022

Senior Member

Bio

Digital VLSI Design

Personal Details

Male
Associate Professor , Jaypee University of Engeenering & Technology, Guna
Jaypee University of Engineering and Technology, A-B Road, Raghogarh

Ph.D

Indian Institute of Technology Roorkee 2013

Associate Professor Jul 2013 – Present

Jaypee University of Engeenering & Technology, Guna | Department of Electronics and Communication Engineering

Related Profiles

Experts (19623+)

View All

Assistant Professor

Assistant Professor

N/A

Assistant Professor

Assistant Professor

Doctor

Assistant Professor (Grade-I)

Dr N PRAKASH

Assistant Professor

Mr Mrinmoy Sadhukhan

Research Scholar

Mr Haranath Rakshit

Junior Research Fellow

Organisations (81+)

View All

Mr ARUN ARYA

Assistant Professor (Grade-II)

Dr Sandeep Arya

Assistant Professor

Dr Bhagat Singh

Associate Professor

Dr Bali Ram Gupta

Assistant Professor (Senior Grade)

Dr Vaibhav Bisht

Assistant Professor

Dr Amit Kumar Srivastava

Assistant Professor

Dr AMIT KUMAR

Assistant Professor - Senior Scale

Dr Amiya Kumar Sahoo

Assistant Professor (Grade-II)

Dr Ajay Kumar

Assistant Professor

Dr Abhishek Shukla

Assistant Professor

Co-Authors (7)

Dr Anurag Mahajan

N/A

Dr Durgesh Nandan

Symbiosis Institute of Technology

Dr Ramakant

Mahindra University, Hyderabad

Dr Ritesh Kumar Mishra

National Institute of Technology Patna

Dr Sanjay Vidhyadharan

Birla Institute of Technology and Science

Dr Surya Shankar Dan

Birla Institute of Technology and Science

Prof Sudeb Dasgupta

Indian Institute of Technology Roorkee

Scholarly Work

No Data Found

There is currently nothing to display here.

DESIGN AND ANALYSIS OF AN EFFICIENT ARCHITECTURE OF LOGARITHMIC MULTIPLIER AND ITS APPLICATIONS

University Jaypee University of Engeenering and Technology

Year 2018

NANO-POROUS CARBON MATERIAL WITH REDOX ADDITIVE ELECTROLYTES FOR THE DEVELOPMENT OF HYBRID SUPERCAPACITOR

University Jaypee University of Engineering & Technology, Guna

Year 2021

Design of RNS Based Efficient Arithmetic Circuits

University Jaypee University of Engineering and Technology, Guna

Year 2022

OBJECT /MOTION DETECTION BASED PUBLIC LIGHTING FIXTURE

1.Dr. Partha Sarthy Banerjee 2. Dr. Deepak Sharma 3.Dr. Manish Kumar Patidar 4.Dr. Jitendra Kanungo 5.Dr. Rajesh Kumar Vishwakarma.

Engineering and Technology Application No. : 368597-001 Filed : 30-07-2022

Published : N/A Published

Scholarly Publications

Synergistic effect of redox couple VO2+/VO2+ with H3PO4 to enhance the supercapacitor performance

Open Access

Article

Year: 2019. Volume: 30 , Issue: 13 , Pages: 12244-12259 .

Authors: Jain D.;Kanungo J.;Tripathi S.K.

10.1007/S10854-019-01583-8

65 years journey of logarithm multiplier

Open Access

article

Year: 2018. Volume: 18 , Pages: 261-266 .

Authors: Durgesh Nandan, Jitendra Kanungo and Mahajan A.

An efficient architecture of iterative logarithm multiplier

Open Access

Article

Year: 2018. Volume: 7 , Issue: 2 , Pages: 24-28 .

Authors: Nandan D.;Kanungo J.;Mahajan A.

10.14419/ijet.v7i2.16.11410

An efficient VLSI architecture design of Leading One Detector

Open Access

article

Year: 2018.

Authors: Jitendra Kanungo

An efficient VLSI architecture design of Leading One Detector

Open Access

journal-article

Year: 2018.

Authors:

Diminished-1 multiplier using modulo adder

Open Access

article

Year: 2018. Volume: 7 , Pages: 31-35 .

Authors: Beerendra Kumar Patel, and Jitendra Kanungo

An efficient VLSI architecture design of Leading One Detector

Open Access

article

Year: 2018.

Authors: Durgesh Nandan, Jitendra Kanungo and Mahajan A.

Diminished-1 multiplier using modulo adder

Open Access

article

Year: 2018.

Authors: Patel B.K.;Kanungo J.

10.14419/ijet.v7i4.20.22117

Showing 17 to 24 of 61 results

Dr Jitendra Kanungo

Expertise

Publications

Publications

Scopus

CrossRef

Google Scholar

Professional Recognition

No Data Found

Community & Membership

Bio

Personal Details

Related Profiles

Experts (19623+)

Organisations (81+)

Co-Authors (7)

Scholarly Work

No Data Found

DESIGN AND ANALYSIS OF AN EFFICIENT ARCHITECTURE OF LOGARITHMIC MULTIPLIER AND ITS APPLICATIONS

NANO-POROUS CARBON MATERIAL WITH REDOX ADDITIVE ELECTROLYTES FOR THE DEVELOPMENT OF HYBRID SUPERCAPACITOR

Design of RNS Based Efficient Arithmetic Circuits

OBJECT /MOTION DETECTION BASED PUBLIC LIGHTING FIXTURE

1.Dr. Partha Sarthy Banerjee 2. Dr. Deepak Sharma 3.Dr. Manish Kumar Patidar 4.Dr. Jitendra Kanungo 5.Dr. Rajesh Kumar Vishwakarma.

Scholarly Publications

Synergistic effect of redox couple VO<SUP>2+</SUP>/VO<sub>2</sub><SUP>+</SUP> with H<sub>3</sub>PO<sub>4</sub> to enhance the supercapacitor performance

65 years journey of logarithm multiplier

An efficient architecture of iterative logarithm multiplier

An efficient VLSI architecture design of Leading One Detector

An efficient VLSI architecture design of Leading One Detector

Diminished-1 multiplier using modulo adder

An efficient VLSI architecture design of Leading One Detector

Diminished-1 multiplier using modulo adder